ixhssacccommon_p.h

有关ARM开发板上的IXP400网络驱动程序的源码以。

/**
 * @file IxHssAccCommon_p.h
 * 
 * @author Intel Corporation
 * @date 10-DEC-2001
 *
 * @brief This file contains the private API of the HSS Access Common
 * module
 *
 * 
 * @par
 * IXP400 SW Release version 2.1
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright (c) 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * 
 * @par
 * -- End of Copyright Notice --
*/

/**
 * @defgroup IxHssAccCommon_p IxHssAccCommon_p
 *
 * @brief The private API for the HssAccess Common module
 * 
 * @{
 */

#ifndef IXHSSACCCOMMON_P_H
#define IXHSSACCCOMMON_P_H

#include <stdio.h>
#include "IxHssAcc.h"
#include "IxNpeMh.h"

/*
 * Global variables
 */
extern IxHssAccHssPort hssPortMax; /**< Number of HSS ports available */

/**
 * #defines for function return types, etc.
 */

/**
 * @def IX_HSSACC_MAX_CHAN_TIMESLOTS
 *
 * @brief The number of timeslots supported for the channelised
 * service
 */
#define IX_HSSACC_MAX_CHAN_TIMESLOTS 32

/**
 * @def IX_HSSACC_BYTES_PER_WORD
 *
 * @brief Number of bytes per word
 */
#define IX_HSSACC_BYTES_PER_WORD 4

/**
 * @def IX_HSSACC_LUT_BITS_PER_TS
 *
 * @brief The number of bits each HSS timeslot consumes in the HSS Co-p LUT
 */
#define IX_HSSACC_LUT_BITS_PER_TS     2

/**
 * @def IX_HSSACC_LUT_BITS_PER_WORD
 *
 * @brief The number of bits per HSS Co-p LUT word entry
 */
#define IX_HSSACC_LUT_BITS_PER_WORD  32

/**
 * @def IX_HSSACC_LUT_WORDS_PER_LUT
 *
 * @brief The total number of words in the HSS Co-p LUT to represent all
 * timeslots with the HSS TDM stream
 */
#define IX_HSSACC_LUT_WORDS_PER_LUT  ((IX_HSSACC_TSLOTS_PER_HSS_PORT * IX_HSSACC_LUT_BITS_PER_TS) / IX_HSSACC_LUT_BITS_PER_WORD)

/**
 * @def IX_HSSACC_SINGLE_HSS_PORT
 *
 * @brief The max number of ports available when only HSS port 0 is 
 * enabled
 */
#define IX_HSSACC_SINGLE_HSS_PORT  IX_HSSACC_HSS_PORT_1

/**
 * @def IX_HSSACC_DUAL_HSS_PORTS
 *
 * @brief The max number of ports available when both HSS ports are 
 * enabled
 */
#define IX_HSSACC_DUAL_HSS_PORTS  IX_HSSACC_HSS_PORT_MAX

/**
 * @def IX_HSSACC_LUT_TS_MASK
 *
 * @brief The mask used to extract HSS timeslot usage from HSS Co-p LUT 
 * word entry
 */
#define IX_HSSACC_LUT_TS_MASK  	     0x00000003

/* ------------------------------------------
   The following are HSS Co-p related defines
   ------------------------------------------ */
/**
 * @def IX_HSSACC_COM_HSSPCR_FTYPE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FTYPE in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_FTYPE_OFFSET    30

/**
 * @def IX_HSSACC_COM_HSSPCR_FENABLE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FENABLE in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_FENABLE_OFFSET  28

/**
 * @def IX_HSSACC_COM_HSSPCR_FEDGE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FEDGE in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_FEDGE_OFFSET    27

/**
 * @def IX_HSSACC_COM_HSSPCR_DEDGE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for DEDGE in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_DEDGE_OFFSET    26

/**
 * @def IX_HSSACC_COM_HSSPCR_CLKDIR_OFFSET
 *
 * @brief The HSS co-processor register bit offset for CLKDIR in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_CLKDIR_OFFSET   25

/**
 * @def IX_HSSACC_COM_HSSPCR_FRAME_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FRAME in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_FRAME_OFFSET    24

/**
 * @def IX_HSSACC_COM_HSSPCR_HALF_OFFSET
 *
 * @brief The HSS co-processor register bit offset for HALF in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_HALF_OFFSET     21

/**
 * @def IX_HSSACC_COM_HSSPCR_DPOL_OFFSET
 *
 * @brief The HSS co-processor register bit offset for DPOL in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_DPOL_OFFSET     20

/**
 * @def IX_HSSACC_COM_HSSPCR_BITEND_OFFSET
 *
 * @brief The HSS co-processor register bit offset for BITEND in
 * HSSTXPCR/HSSRXPCR
 */
#define IX_HSSACC_COM_HSSPCR_BITEND_OFFSET   19

/**
 * @def IX_HSSACC_COM_HSSPCR_ODRAIN_OFFSET
 *
 * @brief The HSS co-processor register bit offset for ODRAIN in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_ODRAIN_OFFSET   18

/**
 * @def IX_HSSACC_COM_HSSPCR_FBIT_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FBIT in
 * HSSTXPCR/HSSRXPCR 
 */
#define IX_HSSACC_COM_HSSPCR_FBIT_OFFSET     17

/**
 * @def IX_HSSACC_COM_HSSPCR_ENABLE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for ENABLE in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_ENABLE_OFFSET   16

/**
 * @def IX_HSSACC_COM_HSSPCR_56KTYPE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for 56KTYPE in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_56KTYPE_OFFSET  13

/**
 * @def IX_HSSACC_COM_HSSPCR_UTYPE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for UTYPE in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_UTYPE_OFFSET    11

/**
 * @def IX_HSSACC_COM_HSSPCR_FBTYPE_OFFSET
 *
 * @brief The HSS co-processor register bit offset for FBTYPE in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_FBTYPE_OFFSET   10

/**
 * @def IX_HSSACC_COM_HSSPCR_56KEND_OFFSET
 *
 * @brief The HSS co-processor register bit offset for 56KEND in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_56KEND_OFFSET   9

/**
 * @def IX_HSSACC_COM_HSSPCR_56KSEL_OFFSET
 *
 * @brief The HSS co-processor register bit offset for 56KSEL in HSSTXPCR
 */
#define IX_HSSACC_COM_HSSPCR_56KSEL_OFFSET   8

/**
 * @def IX_HSSACC_COM_HSSCCR_HFIFO_OFFSET
 *
 * @brief The HSS co-processor register bit offset for HFIFO in HSSCCR
 */
#define IX_HSSACC_COM_HSSCCR_HFIFO_OFFSET    26

/**
 * @def IX_HSSACC_COM_HSSCCR_LBACK_OFFSET
 *
 * @brief The HSS co-processor register bit offset for LBACK in HSSCCR
 */
#define IX_HSSACC_COM_HSSCCR_LBACK_OFFSET    25

/**
 * @def IX_HSSACC_COM_HSSCCR_COND_OFFSET
 *
 * @brief The HSS co-processor register bit offset for COND in HSSCCR
 */
#define IX_HSSACC_COM_HSSCCR_COND_OFFSET     24

/**
 * @def IX_HSSACC_COM_HSSCLKCR_MAIN_OFFSET
 *
 * @brief The HSS co-processor register bit offset for MAIN in HSSCLKCR
 */
#define IX_HSSACC_COM_HSSCLKCR_MAIN_OFFSET   22 

/**
 * @def IX_HSSACC_COM_HSSCLKCR_NUM_OFFSET