s3c2410.h

2410/vxworks/tornado下的基本实验包括 serial,ramdrv,interrupt,multi-FTP,TCP,UDP-Under the basic experimental

#define ADC_START_BY_RD_DIS	FClrBit(ADCCON, ADCCON_READ_START)
#define ADC_START_BY_RD_EN	(ADCCON_READ_START*1)
#define ADC_START		(1 << 0)

#define UD_SEN			(1 << 8)
#define DOWN_INT		(UD_SEN*0)
#define UP_INT			(UD_SEN*1)
#define YM_SEN			(1 << 7)
#define YM_HIZ			(YM_SEN*0)
#define YM_GND			(YM_SEN*1)
#define YP_SEN			(1 << 6)
#define YP_EXTVLT		(YP_SEN*0)
#define YP_AIN			(YP_SEN*1)
#define XM_SEN			(1 << 5)
#define XM_HIZ			(XM_SEN*0)
#define XM_GND			(XM_SEN*1)
#define XP_SEN			(1 << 4)
#define XP_EXTVLT		(XP_SEN*0)
#define XP_AIN			(XP_SEN*1)
#define XP_PULL_UP		(1 << 3)
#define XP_PULL_UP_EN		(XP_PULL_UP*0)
#define XP_PULL_UP_DIS		(XP_PULL_UP*1)
#define AUTO_PST		(1 << 2)
#define CONVERT_MAN		(AUTO_PST*0)
#define CONVERT_AUTO		(AUTO_PST*1)
#define XP_PST(x)		(x << 0)

/* DMA */
#define DMA_CTL_BASE	0x4b000000
#define bDMA_CTL(Nb,x)	__REG(DMA_CTL_BASE + (0x40*Nb) + (x))
/* DMA channel 0 */
#define DISRC0			bDMA_CTL(0, 0x00)
#define DISRCC0			bDMA_CTL(0, 0x04)
#define DIDST0			bDMA_CTL(0, 0x08)
#define DIDSTC0			bDMA_CTL(0, 0x0c)
#define DCON0			bDMA_CTL(0, 0x10)
#define DSTAT0			bDMA_CTL(0, 0x14)
#define DCSRC0			bDMA_CTL(0, 0x18)
#define DCDST0			bDMA_CTL(0, 0x1c)
#define DMTRIG0			bDMA_CTL(0, 0x20)
/* DMA channel 1 */
#define DISRC1			bDMA_CTL(1, 0x00)
#define DISRCC1			bDMA_CTL(1, 0x04)
#define DIDST1			bDMA_CTL(1, 0x08)
#define DIDSTC1			bDMA_CTL(1, 0x0c)
#define DCON1			bDMA_CTL(1, 0x10)
#define DSTAT1			bDMA_CTL(1, 0x14)
#define DCSRC1			bDMA_CTL(1, 0x18)
#define DCDST1			bDMA_CTL(1, 0x1c)
#define DMTRIG1			bDMA_CTL(1, 0x20)
/* DMA channel 2 */
#define DISRC2			bDMA_CTL(2, 0x00)
#define DISRCC2			bDMA_CTL(2, 0x04)
#define DIDST2			bDMA_CTL(2, 0x08)
#define DIDSTC2			bDMA_CTL(2, 0x0c)
#define DCON2			bDMA_CTL(2, 0x10)
#define DSTAT2			bDMA_CTL(2, 0x14)
#define DCSRC2			bDMA_CTL(2, 0x18)
#define DCDST2			bDMA_CTL(2, 0x1c)
#define DMTRIG2			bDMA_CTL(2, 0x20)
/* DMA channel 3 */
#define DISRC3			bDMA_CTL(3, 0x00)
#define DISRCC3			bDMA_CTL(3, 0x04)
#define DIDST3			bDMA_CTL(3, 0x08)
#define DIDSTC3			bDMA_CTL(3, 0x0c)
#define DCON3			bDMA_CTL(3, 0x10)
#define DSTAT3			bDMA_CTL(3, 0x14)
#define DCSRC3			bDMA_CTL(3, 0x18)
#define DCDST3			bDMA_CTL(3, 0x1c)
#define DMTRIG3			bDMA_CTL(3, 0x20)

/* DISRC, DIDST Control registers */
#define fDMA_BASE_ADDR		Fld(30, 0)      /* base address of src/dst data */
#define DMA_BASE_ADDR(x)	FInsrt(x, fDMA_BASE_ADDR)
#define LOC_SRC			(1 << 1)	/* select the location of source */
#define ON_AHB			(LOC_SRC*0)
#define ON_APB			(LOC_SRC*1)
#define ADDR_MODE		(1 << 0)       /* select the address increment */
#define ADDR_INC		(ADDR_MODE*0)
#define ADDR_FIX		(ADDR_MODE*1)

/* DCON Definitions */
#define DCON_MODE		(1 << 31)	/* 0: demand, 1: handshake */
#define DEMAND_MODE		(DCON_MODE*0)
#define HS_MODE			(DCON_MODE*1)
#define DCON_SYNC		(1 << 30)       /* sync to 0:PCLK, 1:HCLK */
#define SYNC_PCLK		(DCON_SYNC*0)
#define SYNC_HCLK		(DCON_SYNC*1)
#define DCON_INT		(1 << 29)
#define POLLING_MODE		(DCON_INT*0)
#define SINT_MODE		(DCON_INT*1)
#define DCON_TSZ		(1 << 28)	/* tx size 0: a unit, 1: burst */
#define TSZ_UNIT		(DCON_TSZ*0)
#define TSZ_BURST		(DCON_TSZ*1)
#define DCON_SERVMODE		(1 << 27)	/* 0: single, 1: whole service */
#define SINGLE_SERVICE		(DCON_SERVMODE*0)
#define WHOLE_SERVICE		(DCON_SERVMODE*1)
#define fDCON_HWSRC		Fld(3, 24)	/* select request source */
#define CH0_nXDREQ0		0
#define CH0_UART0		1
#define CH0_MMC			2
#define CH0_TIMER		3
#define CH0_USBEP1		4
#define CH1_nXDREQ1		0
#define CH1_UART1		1
#define CH1_I2SSDI		2
#define CH1_SPI			3
#define CH1_USBEP2		4
#define CH2_I2SSDO		0
#define CH2_I2SSDI		1
#define CH2_MMC			2
#define CH2_TIMER		3
#define CH2_USBEP3		4
#define CH3_UART2		0
#define CH3_MMC			1
#define CH3_SPI			2
#define CH3_TIMER		3
#define CH3_USBEP4		4
#define HWSRC(x)		FInsrt(x, fDCON_HWSRC)
#define DCON_SWHW_SEL		(1 << 23)	/* DMA src 0: s/w 1: h/w */
#define DMA_SRC_SW		(DCON_SWHW_SEL*0)
#define DMA_SRC_HW		(DCON_SWHW_SEL*1)
#define DCON_RELOAD		(1 << 22)	/* set auto-reload */
#define SET_ATRELOAD		(DCON_RELOAD*0)
#define CLR_ATRELOAD		(DCON_RELOAD*1)
#define fDCON_DSZ		Fld(2, 20)
#define DSZ_BYTE		0
#define DSZ_HALFWORD		1
#define DSZ_WORD		2
#define DSZ(x)			FInsrt(x, fDCON_DSZ)
#define readDSZ(x)		FExtr(x, fDCON_DSZ)
#define fDCON_TC		Fld(20,0)
#define TX_CNT(x)		FInsrt(x, fDCON_TC)
/* STATUS Register Definitions  */
#define fDSTAT_ST		Fld(2,20)	/* Status of DMA Controller */
#define fDSTAT_TC		Fld(20,0)	/* Current value of transfer count */
#define DMA_STATUS(chan)	FExtr((DSTAT0 + (0x20 * chan)), fDSTAT_ST)
#define DMA_BUSY		(1 << 0)
#define DMA_READY		(0 << 0)
#define DMA_CURR_TC(chan)	FExtr((DSTAT0 + (0x20 * chan)), fDSTAT_TC)      
/* DMA Trigger Register Definitions */
#define DMASKTRIG_STOP		(1 << 2)	/* Stop the DMA operation */
#define DMA_STOP		(DMASKTRIG_STOP*1)
#define DMA_STOP_CLR		(DMASKTRIG_STOP*0)
#define DMASKTRIG_ONOFF		(1 << 1)	/* DMA channel on/off */
#define CHANNEL_ON		(DMASKTRIG_ONOFF*1)
#define CHANNEL_OFF		(DMASKTRIG_ONOFF*0)
#define DMASKTRIG_SW		(1 << 0)	/* Trigger DMA ch. in S/W req. mode */
#define DMA_SW_REQ_CLR		(DMASKTRIG_SW*0)
#define DMA_SW_REQ		(DMASKTRIG_SW*1)

/* IIS Bus Interface */
#define IIS_CTL_BASE		0x55000000
#define bIIS_CTL(Nb)		__REG(IIS_CTL_BASE + (Nb))
#define IISCON			bIIS_CTL(0x00)
#define IISMOD			bIIS_CTL(0x04)
#define IISPSR			bIIS_CTL(0x08)
#define IISFIFOC		bIIS_CTL(0x0c)
#define IISFIFOE		bIIS_CTL(0x10)

#define IISCON_CH_RIGHT (1 << 8)        /* Right channel */
#define IISCON_CH_LEFT  (0 << 8)        /* Left channel */
#define IISCON_TX_RDY   (1 << 7)        /* Transmit FIFO is ready(not empty) */
#define IISCON_RX_RDY   (1 << 6)        /* Receive FIFO is ready (not full) */
#define IISCON_TX_DMA   (1 << 5)        /* Transmit DMA service reqeust */
#define IISCON_RX_DMA   (1 << 4)        /* Receive DMA service reqeust */
#define IISCON_TX_IDLE  (1 << 3)        /* Transmit Channel idle */
#define IISCON_RX_IDLE  (1 << 2)        /* Receive Channel idle */
#define IISCON_PRESCALE (1 << 1)        /* IIS Prescaler Enable */
#define IISCON_EN       (1 << 0)        /* IIS enable(start) */

#define IISMOD_SEL_MA   (0 << 8)        /* Master mode
					                                              (IISLRCK, IISCLK are Output) */
#define IISMOD_SEL_SL   (1 << 8)        /* Slave mode
					                                              (IISLRCK, IISCLK are Input) */
#define fIISMOD_SEL_TR  Fld(2, 6)       /* Transmit/Receive mode */
#define IISMOD_SEL_TR   FMsk(fIISMOD_SEL_TR)
#define IISMOD_SEL_NO   FInsrt(0x0, fIISMOD_SEL_TR)     /* No Transfer */
#define IISMOD_SEL_RX   FInsrt(0x1, fIISMOD_SEL_TR)     /* Receive */
#define IISMOD_SEL_TX   FInsrt(0x2, fIISMOD_SEL_TR)     /* Transmit */
#define IISMOD_SEL_BOTH FInsrt(0x3, fIISMOD_SEL_TR)     /* Tx & Rx */
#define IISMOD_CH_RIGHT (0 << 5)        /* high for right channel */
#define IISMOD_CH_LEFT  (1 << 5)        /* high for left channel */
#define IISMOD_FMT_IIS  (0 << 4)        /* IIS-compatible format */
#define IISMOD_FMT_MSB  (1 << 4)        /* MSB(left)-justified format */
#define IISMOD_BIT_8    (0 << 3)        /* Serial data bit/channel is 8 bit*/
#define IISMOD_BIT_16   (1 << 3)        /* Serial data bit/channel is 16 bit*/
#define IISMOD_FREQ_256 (0 << 2)        /* Master clock freq = 256 fs */
#define IISMOD_FREQ_384 (1 << 2)        /* Master clock freq = 384 fs */
#define fIISMOD_SFREQ   Fld(2, 0)       /* Serial bit clock frequency */
#define IISMOD_SFREQ    FMsk(fIISMOD_SFREQ)     /* fs = sampling frequency */
#define IISMOD_SFREQ_16 FInsrt(0x0, fIISMOD_SFREQ)      /* 16 fs */
#define IISMOD_SFREQ_32 FInsrt(0x1, fIISMOD_SFREQ)      /* 32 fs */
#define IISMOD_SFREQ_48 FInsrt(0x2, fIISMOD_SFREQ)      /* 48 fs */

#define fIISPSR_A       Fld(5, 5)       /* Prescaler Control A */
#define IISPSR_A(x)     FInsrt((x), fIISPSR_A)
#define fIISPSR_B       Fld(5, 0)       /* Prescaler Control B */
#define IISPSR_B(x)     FInsrt((x), fIISPSR_B)  

#define IISFCON_TX_NORM (0 << 15)       /* Transmit FIFO access mode: normal */
#define IISFCON_TX_DMA  (1 << 15)       /* Transmit FIFO access mode: DMA */
#define IISFCON_RX_NORM (0 << 14)       /* Receive FIFO access mode: normal */
#define IISFCON_RX_DMA  (1 << 14)       /* Receive FIFO access mode: DMA */
#define IISFCON_TX_EN   (1 << 13)        /* Transmit FIFO enable */
#define IISFCON_RX_EN   (1 << 12)        /* Recevice FIFO enable */
#define fIISFCON_TX_CNT Fld(6, 6)       /* Tx FIFO data count (Read-Only) */
#define IISFCON_TX_CNT  FMsk(fIISFCON_TX_CNT)
#define fIISFCON_RX_CNT Fld(6, 0)       /* Rx FIFO data count (Read-Only) */
#define IISFCON_RX_CNT  FMsk(fIISFCON_RX_CNT)

/* USB Device - Little Endian : 
 * (B) : byte(8 bit) access
 * (W) : word(32 bit) access
 */
#define bUD(Nb)		__REG(0x52000000 + (Nb))
#define UD_FUNC		bUD(0x140) /* Function address  (B)                       */
#define UD_PWR		bUD(0x144) /* Power management (B)                        */
#define UD_INT		bUD(0x148) /* Endpoint interrupt pending/clear (B)        */
#define UD_USBINT	bUD(0x158) /* USB interrupt pending/clear (B)             */
#define UD_INTE		bUD(0x15c) /* Endpoint interrupt enable (B)               */
#define UD_USBINTE	bUD(0x16c) /* USB interrupt enable (B)                    */
#define UD_FRAMEL	bUD(0x170) /* Frame number low-byte (B)                   */
#define UD_FRAMEH	bUD(0x174) /* Frame number high-byte (B)                  */
#define UD_INDEX	bUD(0x178) /* Index (B)                                   */
#define UD_FIFO0	bUD(0x1c0) /* Endpoint 0 FIFO (B)                         */
#define UD_FIFO1	bUD(0x1c4) /* Endpoint 1 FIFO (B)                         */
#define UD_FIFO2	bUD(0x1c8) /* Endpoint 2 FIFO (B)                         */
#define UD_FIFO3	bUD(0x1cc) /* Endpoint 3 FIFO (B)                         */
#define UD_FIFO4	bUD(0x1d0) /* Endpoint 4 FIFO (B)                         */
#define UD_DMACON1	bUD(0x200) /* Endpoint 1 DMA control (B)                  */
#define UD_DMAUC1	bUD(0x204) /* Endpoint 1 DMA unit counter (B)             */
#define UD_DMAFC1	bUD(0x208) /* Endpoint 1 DMA FIFO counter                 */
#define UD_DMATCL1	bUD(0x20c) /* Endpoint 1 DMA Transfer counter low-byte    */
#define UD_DMATCM1	bUD(0x210) /* Endpoint 1 DMA Transfer counter middle-byte */
#define UD_DMATCH1	bUD(0x214) /* Endpoint 1 DMA Transfer counter high-byte   */
#define UD_DMACON2	bUD(0x218) /* Endpoint 2 DMA control (B)                  */
#define UD_DMAUC2	bUD(0x21c) /* Endpoint 2 DMA unit counter (B)             */
#define UD_DMAFC2	bUD(0x220) /* Endpoint 2 DMA FIFO counter                 */
#define UD_DMATCL2	bUD(0x224) /* Endpoint 2 DMA Transfer counter low-byte    */
#define UD_DMATCM2	bUD(0x228) /* Endpoint 2 DMA Transfer counter middle-byte */
#define UD_DMATCH2	bUD(0x22c) /* Endpoint 2 DMA Transfer counter high-byte   */
#define UD_DMACON3	bUD(0x240) /* Endpoint 3 DMA control (B)                  */
#define UD_DMAUC3	bUD(0x244) /* Endpoint 3 DMA unit counter (B)             */
#define UD_DMAFC3	bUD(0x248) /* Endpoint 3 DMA FIFO counter                 */
#define UD_DMATCL3	bUD(0x24c) /* Endpoint 3 DMA Transfer counter low-byte    */
#define UD_DMATCM3	bUD(0x250) /* Endpoint 3 DMA Transfer counter middle-byte */
#define UD_DMATCH3	bUD(0x254) /* Endpoint 3 DMA Transfer counter high-byte   */
#define UD_DMACON4	bUD(0x258) /* Endpoint 4 DMA control (B)                  */
#define UD_DMAUC4	bUD(0x25c) /* Endpoint 4 DMA unit counter (B)             */
#define UD_DMAFC4	bUD(0x260) /* Endpoint 4 DMA FIFO counter                 */
#define UD_DMATCL4	bUD(0x264) /* Endpoint 4 DMA Transfer counter low-byte    */
#define UD_DMATCM4	bUD(0x268) /* Endpoint 4 DMA Transfer counter middle-byte */
#define UD_DMATCH4	bUD(0x26c) /* Endpoint 4 DMA Transfer counter high-byte   */
#define UD_MAXP		bUD(0x180) /* Endpoint MAX Packet                         */
#define UD_ICSR1	bUD(0x184) /* EP In control status register 1 (B)         */
#define UD_ICSR2	bUD(0x188) /* EP In control status register 2 (B)         */
#define UD_OCSR1	bUD(0x190) /* EP Out control status register 1 (B)        */
#define UD_OCSR2	bUD(0x194) /* EP Out control status register 2 (B)        */
#define UD_OFCNTL	bUD(0x198) /* EP Out Write counter low-byte (B)           */
#define UD_OFCNTH	bUD(0x19c) /* EP Out Write counter high-byte (B)          */

#define UD_FUNC_UD	(1 << 7)
#define fUD_FUNC_ADDR	Fld(7,0)	/* USB Device Addr. assigned by host */
#define UD_FUNC_ADDR	FMsk(fUD_FUNC_ADDR)

#define UD_PWR_ISOUP	(1<<7) /* R/W */
#define UD_PWR_RESET	(1<<3) /* R   */
#define UD_PWR_RESUME	(1<<2) /* R/W */
#define UD_PWR_SUSPND	(1<<1) /* R   */
#define UD_PWR_ENSUSPND	(1<<0) /* R/W */

#define UD_PWR_DEFAULT	0x00

#define UD_INT_EP4	(1<<4)	/* R/W (clear only) */
#define UD_INT_EP3	(1<<3)	/* R/W (clear only) */
#define UD_INT_EP2	(1<<2)	/* R/W (clear only) */
#define UD_INT_EP1	(1<<1)	/* R/W (clear only) */
#define UD_INT_EP0	(1<<0)	/* R/W (clear only) */

#define UD_USBINT_RESET	(1<<2) /* R/W (clear only) */
#define UD_USBINT_RESUM	(1<<1) /* R/W (clear only) */
#define UD_USBINT_SUSPND (1<<0) /* R/W (clear only)*/

#define UD_INTE_EP4	(1<<4) /* R/W */
#define UD_INTE_EP3	(1<<3) /* R/W */
#define UD_INTE_EP2	(1<<2) /* R/W */
#define UD_INTE_EP1	(1<<1) /* R/W */
#define UD_INTE_EP0	(1<<0) /* R/W */

#define UD_USBINTE_RESET	(1<<2) /* R/W */
#define UD_USBINTE_SUSPND	(1<<0) /* R/W */

#define fUD_FRAMEL_NUM	Fld(8,0) /* R */
#define UD_FRAMEL_NUM	FMsk(fUD_FRAMEL_NUM)

#define fUD_FRAMEH_NUM	Fld(8,0) /* R */
#define UD_FRAMEH_NUM	FMsk(fUD_FRAMEH_NUM)

#define UD_INDEX_EP0	(0x00)
#define UD_INDEX_EP1	(0x01) 
#define UD_INDEX_EP2	(0x02) 
#define UD_INDEX_EP3	(0x03) 
#define UD_INDEX_EP4	(0x04) 

#define UD_ICSR1_CLRDT	(1<<6)   /* R/W              */
#define UD_ICSR1_SENTSTL (1<<5)  /* R/W (clear only) */
#define UD_ICSR1_SENDSTL (1<<4)  /* R/W              */
#define UD_ICSR1_FFLUSH (1<<3)   /* W	(set only)   */
#define UD_ICSR1_UNDRUN  (1<<2)  /* R/W (clear only) */
#define UD_ICSR1_PKTRDY	 (1<<0)  /* R/W (set only)   */

#define UD_ICSR2_AUTOSET (1<<7) /* R/