s3c2410.h

2410/vxworks/tornado下的基本实验包括 serial,ramdrv,interrupt,multi-FTP,TCP,UDP-Under the basic experimental

#define GPIO_H2				MAKE_GPIO_NUM(PORTH_OFS, 2)
#define GPIO_H3				MAKE_GPIO_NUM(PORTH_OFS, 3)
#define GPIO_H4				MAKE_GPIO_NUM(PORTH_OFS, 4)
#define GPIO_H5				MAKE_GPIO_NUM(PORTH_OFS, 5)
#define GPIO_H6				MAKE_GPIO_NUM(PORTH_OFS, 6)
#define GPIO_H7				MAKE_GPIO_NUM(PORTH_OFS, 7)
#define GPIO_H8				MAKE_GPIO_NUM(PORTH_OFS, 8)
#define GPIO_H9				MAKE_GPIO_NUM(PORTH_OFS, 9)
#define GPIO_H10			MAKE_GPIO_NUM(PORTH_OFS, 10)

#define GPIO_MODE_TOUT			GPIO_MODE_ALT0
#define GPIO_MODE_nXBACK		GPIO_MODE_ALT0
#define GPIO_MODE_nXBREQ		GPIO_MODE_ALT0
#define GPIO_MODE_nXDACK		GPIO_MODE_ALT0
#define GPIO_MODE_nXDREQ		GPIO_MODE_ALT0
#define GPIO_MODE_LEND			GPIO_MODE_ALT0
#define GPIO_MODE_VCLK			GPIO_MODE_ALT0
#define GPIO_MODE_VLINE			GPIO_MODE_ALT0
#define GPIO_MODE_VFRAME		GPIO_MODE_ALT0
#define GPIO_MODE_VM			GPIO_MODE_ALT0
#define GPIO_MODE_LCDVF			GPIO_MODE_ALT0
#define GPIO_MODE_VD			GPIO_MODE_ALT0
#define GPIO_MODE_IICSDA		GPIO_MODE_ALT0
#define GPIO_MODE_IICSCL		GPIO_MODE_ALT0
#define GPIO_MODE_SPICLK		GPIO_MODE_ALT0
#define GPIO_MODE_SPIMOSI		GPIO_MODE_ALT0
#define GPIO_MODE_SPIMISO		GPIO_MODE_ALT0
#define GPIO_MODE_SDDAT			GPIO_MODE_ALT0
#define GPIO_MODE_SDCMD			GPIO_MODE_ALT0
#define GPIO_MODE_SDCLK			GPIO_MODE_ALT0
#define GPIO_MODE_I2SSDO		GPIO_MODE_ALT0
#define GPIO_MODE_I2SSDI		GPIO_MODE_ALT0
#define GPIO_MODE_CDCLK			GPIO_MODE_ALT0
#define GPIO_MODE_I2SSCLK		GPIO_MODE_ALT0
#define GPIO_MODE_I2SLRCK		GPIO_MODE_ALT0
#define GPIO_MODE_I2SSDI_ABNORMAL	GPIO_MODE_ALT1
#define GPIO_MODE_nSS			GPIO_MODE_ALT1
#define GPIO_MODE_EINT			GPIO_MODE_ALT0
#define GPIO_MODE_nYPON			GPIO_MODE_ALT1
#define GPIO_MODE_YMON			GPIO_MODE_ALT1
#define GPIO_MODE_nXPON			GPIO_MODE_ALT1
#define GPIO_MODE_XMON			GPIO_MODE_ALT1
#define GPIO_MODE_UART			GPIO_MODE_ALT0	
#define GPIO_MODE_TCLK_ABNORMAL		GPIO_MODE_ALT1
#define GPIO_MODE_SPICLK_ABNORMAL	GPIO_MODE_ALT1
#define GPIO_MODE_SPIMOSI_ABNORMAL	GPIO_MODE_ALT1
#define GPIO_MODE_SPIMISO_ABNORMAL	GPIO_MODE_ALT1
#define GPIO_MODE_LCD_PWRDN		GPIO_MODE_ALT1

/* UART */
#define UART_CTL_BASE		0x50000000
#define UART0_CTL_BASE		UART_CTL_BASE
#define UART1_CTL_BASE		UART_CTL_BASE + 0x4000
#define UART2_CTL_BASE		UART_CTL_BASE + 0x8000
#define bUART(x, Nb)		__REG(UART_CTL_BASE + (x)*0x4000 + (Nb))
/* Offset */
#define oULCON			0x00	/* R/W, UART line control register */
#define oUCON			0x04	/* R/W, UART control register */
#define oUFCON			0x08	/* R/W, UART FIFO control register */
#define oUMCON			0x0C	/* R/W, UART modem control register */
#define oUTRSTAT		0x10	/* R  , UART Tx/Rx status register */
#define oUERSTAT		0x14	/* R  , UART Rx error status register */
#define oUFSTAT			0x18	/* R  , UART FIFO status register */
#define oUMSTAT			0x1C	/* R  , UART Modem status register */
#define oUTXHL			0x20	/*   W, UART transmit(little-end) buffer */
#define oUTXHB			0x23	/*   W, UART transmit(big-end) buffer */
#define oURXHL			0x24	/* R  , UART receive(little-end) buffer */
#define oURXHB			0x27	/* R  , UART receive(big-end) buffer */
#define oUBRDIV			0x28	/* R/W, Baud rate divisor register */
/* Registers */
#define ULCON0			bUART(0, oULCON)
#define UCON0			bUART(0, oUCON)
#define UFCON0			bUART(0, oUFCON)
#define UMCON0			bUART(0, oUMCON)
#define UTRSTAT0		bUART(0, oUTRSTAT)
#define UERSTAT0		bUART(0, oUERSTAT)
#define UFSTAT0			bUART(0, oUFSTAT)
#define UMSTAT0			bUART(0, oUMSTAT)
#define UTXH0			bUART(0, oUTXHL)
#define URXH0			bUART(0, oURXHL)
#define UBRDIV0			bUART(0, oUBRDIV)
#define ULCON1			bUART(1, oULCON)
#define UCON1			bUART(1, oUCON)
#define UFCON1			bUART(1, oUFCON)
#define UMCON1			bUART(1, oUMCON)
#define UTRSTAT1		bUART(1, oUTRSTAT)
#define UERSTAT1		bUART(1, oUERSTAT)
#define UFSTAT1			bUART(1, oUFSTAT)
#define UMSTAT1			bUART(1, oUMSTAT)
#define UTXH1			bUART(1, oUTXHL)
#define URXH1			bUART(1, oURXHL)
#define UBRDIV1			bUART(1, oUBRDIV)
#define ULCON2			bUART(2, oULCON)
#define UCON2			bUART(2, oUCON)
#define UFCON2			bUART(2, oUFCON)
#define UMCON2			bUART(2, oUMCON)
#define UTRSTAT2		bUART(2, oUTRSTAT)
#define UERSTAT2		bUART(2, oUERSTAT)
#define UFSTAT2			bUART(2, oUFSTAT)
#define UMSTAT2			bUART(2, oUMSTAT)
#define UTXH2			bUART(2, oUTXHL)
#define URXH2			bUART(2, oURXHL)
#define UBRDIV2			bUART(2, oUBRDIV)

/* Interrupts */
#define INT_CTL_BASE		0x4A000000
#define INTBASE			__REG(INT_CTL_BASE)
#define bINTCTL(Nb)		__REG(INT_CTL_BASE + (Nb))
/* Offset */
#define oSRCPND			0x00
#define oINTMOD			0x04
#define oINTMSK			0x08
#define oPRIORITY		0x0C
#define oINTPND			0x10
#define oINTOFFSET		0x14
#define oSUBSRCPND		0x18
#define oINTSUBMSK		0x1C
/* Registers */
#define SRCPND			bINTCTL(oSRCPND)
#define INTMOD			bINTCTL(oINTMOD)
#define INTMSK			bINTCTL(oINTMSK)
#define PRIORITY		bINTCTL(oPRIORITY)
#define INTPND			bINTCTL(oINTPND)
#define INTOFFSET		bINTCTL(oINTOFFSET)
#define SUBSRCPND		bINTCTL(oSUBSRCPND)
#define INTSUBMSK		bINTCTL(oINTSUBMSK)

#define INT_ADCTC		(1 << 31)	/* ADC EOC interrupt */
#define INT_RTC			(1 << 30)	/* RTC alarm interrupt */
#define INT_SPI1		(1 << 29)	/* UART1 transmit interrupt */
#define INT_UART0		(1 << 28)	/* UART0 transmit interrupt */
#define INT_IIC			(1 << 27)	/* IIC interrupt */
#define INT_USBH		(1 << 26)	/* USB host interrupt */
#define INT_USBD		(1 << 25)	/* USB device interrupt */
#define INT_RESERVED24		(1 << 24)
#define INT_UART1		(1 << 23)	/* UART1 receive interrupt */
#define INT_SPI0		(1 << 22)	/* SPI interrupt */
#define INT_MMC			(1 << 21)	/* MMC interrupt */
#define INT_DMA3		(1 << 20)	/* DMA channel 3 interrupt */
#define INT_DMA2		(1 << 19)	/* DMA channel 2 interrupt */
#define INT_DMA1		(1 << 18)	/* DMA channel 1 interrupt */
#define INT_DMA0		(1 << 17)	/* DMA channel 0 interrupt */
#define INT_LCD			(1 << 16)	/* reserved for future use */
#define INT_UART2		(1 << 15)	/* UART 2 interrupt  */
#define INT_TIMER4		(1 << 14)	/* Timer 4 interrupt */
#define INT_TIMER3		(1 << 13)	/* Timer 3 interrupt */
#define INT_TIMER2		(1 << 12)	/* Timer 2 interrupt */
#define INT_TIMER1		(1 << 11)	/* Timer 1 interrupt */
#define INT_TIMER0		(1 << 10)	/* Timer 0 interrupt */
#define INT_WDT			(1 << 9)	/* Watch-Dog timer interrupt */
#define INT_TICK		(1 << 8)	/* RTC time tick interrupt  */
#define INT_nBAT_FLT		(1 << 7)
#define INT_RESERVED6		(1 << 6)	/* Reserved for future use */
#define INT_EINT8_23		(1 << 5)	/* External interrupt 8 ~ 23 */
#define INT_EINT4_7		(1 << 4)	/* External interrupt 4 ~ 7 */
#define INT_EINT3		(1 << 3)	/* External interrupt 3 */
#define INT_EINT2		(1 << 2)	/* External interrupt 2 */
#define INT_EINT1		(1 << 1)	/* External interrupt 1 */
#define INT_EINT0		(1 << 0)	/* External interrupt 0 */

#define INT_ADC			(1 << 10)
#define INT_TC			(1 << 9)
#define INT_ERR2		(1 << 8)
#define INT_TXD2		(1 << 7)
#define INT_RXD2		(1 << 6)
#define INT_ERR1		(1 << 5)
#define INT_TXD1		(1 << 4)
#define INT_RXD1		(1 << 3)
#define INT_ERR0		(1 << 2)
#define INT_TXD0		(1 << 1)
#define INT_RXD0		(1 << 0)

/* Real Time Clock */
/* Registers */
#define bRTC(Nb)		__REG(0x57000000 + (Nb))
#define RTCCON			bRTC(0x40)
#define TICNT			bRTC(0x44)
#define RTCALM			bRTC(0x50)
#define ALMSEC			bRTC(0x54)
#define ALMMIN			bRTC(0x58)
#define ALMHOUR			bRTC(0x5c)
#define ALMDAY			bRTC(0x60)
#define ALMMON			bRTC(0x64)
#define ALMYEAR			bRTC(0x68)
#define RTCRST			bRTC(0x6c)
#define BCDSEC			bRTC(0x70)
#define BCDMIN			bRTC(0x74)
#define BCDHOUR			bRTC(0x78)
#define BCDDATE			bRTC(0x7c)
#define BCDDAY			bRTC(0x80)
#define BCDMON			bRTC(0x84)
#define BCDYEAR			bRTC(0x88)
/* Fields */
#define fRTC_SEC		Fld(7,0)
#define fRTC_MIN		Fld(7,0)
#define fRTC_HOUR		Fld(6,0)
#define fRTC_DAY		Fld(6,0)
#define fRTC_DATE		Fld(2,0)
#define fRTC_MON		Fld(5,0)
#define fRTC_YEAR		Fld(8,0)
/* Mask */
#define Msk_RTCSEC		FMsk(fRTC_SEC)
#define Msk_RTCMIN		FMsk(fRTC_MIN)
#define Msk_RTCHOUR		FMsk(fRTC_HOUR)
#define Msk_RTCDAY		FMsk(fRTC_DAY)
#define Msk_RTCDATE		FMsk(fRTC_DATE)
#define Msk_RTCMON		FMsk(fRTC_MON)
#define Msk_RTCYEAR		FMsk(fRTC_YEAR)
/* bits */
#define RTCCON_EN		(1 << 0) /* RTC Control Enable */
#define RTCCON_CLKSEL		(1 << 1) /* BCD clock as XTAL 1/2^25 clock */
#define RTCCON_CNTSEL		(1 << 2) /* 0: Merge BCD counters */
#define RTCCON_CLKRST		(1 << 3) /* RTC clock count reset */

/* RTC Alarm */
#define RTCALM_GLOBAL		(1 << 6) /* Global alarm enable */
#define RTCALM_YEAR		(1 << 5) /* Year alarm enable */
#define RTCALM_MON		(1 << 4) /* Month alarm enable */
#define RTCALM_DAY		(1 << 3) /* Day alarm enable */
#define RTCALM_HOUR		(1 << 2) /* Hour alarm enable */
#define RTCALM_MIN		(1 << 1) /* Minute alarm enable */
#define RTCALM_SEC		(1 << 0) /* Second alarm enable */
#define RTCALM_EN		(RTCALM_GLOBAL | RTCALM_YEAR | RTCALM_MON |\
				RTCALM_DAY | RTCALM_HOUR | RTCALM_MIN |\
				RTCALM_SEC)
#define RTCALM_DIS		(~RTCALM_EN)

/* PWM Timer */
#define bPWM_TIMER(Nb)		__REG(0x51000000 + (Nb))
#define bPWM_BUFn(Nb,x)		bPWM_TIMER(0x0c + (Nb)*0x0c + (x))
/* Registers */
#define TCFG0			bPWM_TIMER(0x00)
#define TCFG1			bPWM_TIMER(0x04)
#define TCON			bPWM_TIMER(0x08)
#define TCNTB0			bPWM_BUFn(0,0x0)
#define TCMPB0			bPWM_BUFn(0,0x4)
#define TCNTO0			bPWM_BUFn(0,0x8)
#define TCNTB1			bPWM_BUFn(1,0x0)
#define TCMPB1			bPWM_BUFn(1,0x4)
#define TCNTO1			bPWM_BUFn(1,0x8)
#define TCNTB2			bPWM_BUFn(2,0x0)
#define TCMPB2			bPWM_BUFn(2,0x4)
#define TCNTO2			bPWM_BUFn(2,0x8)
#define TCNTB3			bPWM_BUFn(3,0x0)
#define TCMPB3			bPWM_BUFn(3,0x4)
#define TCNTO3			bPWM_BUFn(3,0x8)
#define TCNTB4			bPWM_BUFn(4,0x0)
#define TCNTO4			bPWM_BUFn(4,0x4)
/* Fields */
#define fTCFG0_DZONE		Fld(8,16)	/* the dead zone length (= timer 0) */
#define fTCFG0_PRE1		Fld(8,8)	/* prescaler value for time 2,3,4 */
#define fTCFG0_PRE0		Fld(8,0)        /* prescaler value for time 0,1 */
#define fTCON_TIMER0	Fld(5,0)
#define fTCON_TIMER1	Fld(4,8)
#define fTCON_TIMER2	Fld(4,12)
#define fTCON_TIMER3	Fld(4,16)
#define fTCON_TIMER4	Fld(4,20)

/* bits */
#define TCFG0_DZONE(x)		FInsrt((x), fTCFG0_DZONE)
#define TCFG0_PRE1(x)		FInsrt((x), fTCFG0_PRE1)
#define TCFG0_PRE0(x)		FInsrt((x), fTCFG0_PRE0)

#define TCON_4_AUTO		(1 << 22)	/* auto reload on/off for Timer 4 */
#define TCON_4_UPDATE		(1 << 21)	/* manual Update TCNTB4 */
#define TCON_4_ONOFF		(1 << 20)	/* 0: Stop, 1: start Timer 4 */
#define COUNT_4_ON		(TCON_4_ONOFF*1)
#define COUNT_4_OFF		(TCON_4_ONOFF*0)
#define TCON_3_AUTO     (1 << 19)       /* auto reload on/off for Timer 3 */
#define TCON_3_INVERT   (1 << 18)       /* 1: Inverter on for TOUT3 */
#define TCON_3_MAN      (1 << 17)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_3_ONOFF    (1 << 16)       /* 0: Stop, 1: start Timer 3 */
#define TCON_2_AUTO     (1 << 15)       /* auto reload on/off for Timer 3 */
#define TCON_2_INVERT   (1 << 14)       /* 1: Inverter on for TOUT3 */
#define TCON_2_MAN      (1 << 13)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_2_ONOFF    (1 << 12)       /* 0: Stop, 1: start Timer 3 */
#define TCON_1_AUTO     (1 << 11)       /* auto reload on/off for Timer 3 */
#define TCON_1_INVERT   (1 << 10)       /* 1: Inverter on for TOUT3 */
#define TCON_1_MAN      (1 << 9)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_1_ONOFF    (1 << 8)       /* 0: Stop, 1: start Timer 3 */
#define TCON_0_AUTO     (1 << 3)       /* auto reload on/off for Timer 3 */
#define TCON_0_INVERT   (1 << 2)       /* 1: Inverter on for TOUT3 */
#define TCON_0_MAN      (1 << 1)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_0_ONOFF    (1 << 0)       /* 0: Stop, 1: start Timer 3 */

#define TIMER3_ATLOAD_ON        (TCON_3_AUTO*1)
#define TIMER3_ATLAOD_OFF       FClrBit(TCON, TCON_3_AUTO)
#define TIMER3_IVT_ON   (TCON_3_INVERT*1)
#define TIMER3_IVT_OFF  (FClrBit(TCON, TCON_3_INVERT))
#define TIMER3_MANUP    (TCON_3_MAN*1)
#define TIMER3_NOP      (FClrBit(TCON, TCON_3_MAN))
#define TIMER3_ON       (TCON_3_ONOFF*1)
#define TIMER3_OFF      (FClrBit(TCON, TCON_3_ONOFF))
#define TIMER2_ATLOAD_ON        (TCON_2_AUTO*1)
#define TIMER2_ATLAOD_OFF       FClrBit(TCON, TCON_2_AUTO)
#define TIMER2_IVT_ON   (TCON_2_INVERT*1)
#define TIMER2_IVT_OFF  (FClrBit(TCON, TCON_2_INVERT))
#define TIMER2_MANUP    (TCON_2_MAN*1)
#define TIMER2_NOP      (FClrBit(TCON, TCON_2_MAN))
#define TIMER2_ON       (TCON_2_ONOFF*1)
#define TIMER2_OFF      (FClrBit(TCON, TCON_2_ONOFF))
#define TIMER1_ATLOAD_ON        (TCON_1_AUTO*1)
#define TIMER1_ATLAOD_OFF       FClrBit(TCON, TCON_1_AUTO)
#define TIMER1_IVT_ON   (TCON_1_INVERT*1)
#define TIMER1_IVT_OFF  (FClrBit(TCON, TCON_1_INVERT))
#define TIMER1_MANUP    (TCON_1_MAN*1)
#define TIMER1_NOP      (FClrBit(TCON, TCON_1_MAN))
#define TIMER1_ON       (TCON_1_ONOFF*1)
#define TIMER1_OFF      (FClrBit(TCON, TCON_1_ONOFF))
#define TIMER0_ATLOAD_ON        (TCON_0_AUTO*1)
#define TIMER0_ATLAOD_OFF       FClrBit(TCON, TCON_0_AUTO)
#define TIMER0_IVT_ON   (TCON_0_INVERT*1)
#define TIMER0_IVT_OFF  (FClrBit(TCON, TCON_0_INVERT))
#define TIMER0_MANUP    (TCON_0_MAN*1)
#define TIMER0_NOP      (FClrBit(TCON, TCON_0_MAN))