📄 xianshi.rpt
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LC | | A B | Logic cells that feed LAB 'A':
Pin
43 -> - | - - | <-- CLK
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\luogical experiment\the 8st\pinlvji\xianshi.rpt
xianshi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC22 A
| +----------------------------- LC30 B
| | +--------------------------- LC31 C
| | | +------------------------- LC32 D
| | | | +----------------------- LC26 E
| | | | | +--------------------- LC27 F
| | | | | | +------------------- LC28 G
| | | | | | | +----------------- LC25 Y1
| | | | | | | | +--------------- LC17 Y2
| | | | | | | | | +------------- LC18 Y3
| | | | | | | | | | +----------- LC19 Y4
| | | | | | | | | | | +--------- LC20 Y5
| | | | | | | | | | | | +------- LC21 Y6
| | | | | | | | | | | | | +----- LC23 |05jishuqi:2|Q1
| | | | | | | | | | | | | | +--- LC24 |05jishuqi:2|Q2
| | | | | | | | | | | | | | | +- LC29 |05jishuqi:2|Q3
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC23 -> * * * * * * * * * * * * * * * * | - * | <-- |05jishuqi:2|Q1
LC24 -> * * * * * * * * * * * * * * * * | - * | <-- |05jishuqi:2|Q2
LC29 -> * * * * * * * * * * * * * * * * | - * | <-- |05jishuqi:2|Q3
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- CLK
5 -> * * * * * * * - - - - - - - - - | - * | <-- N0
13 -> * * * * * * * - - - - - - - - - | - * | <-- N1
6 -> * * * * * * * - - - - - - - - - | - * | <-- N2
4 -> * * * - - * * - - - - - - - - - | - * | <-- N3
7 -> * * * * * * * - - - - - - - - - | - * | <-- N4
8 -> * * * * * * * - - - - - - - - - | - * | <-- N5
9 -> * * * * * * * - - - - - - - - - | - * | <-- N6
11 -> * * * - - * * - - - - - - - - - | - * | <-- N7
12 -> - - - - - - - - - - - - - * * * | - * | <-- PR_L
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:e:\luogical experiment\the 8st\pinlvji\xianshi.rpt
xianshi
** EQUATIONS **
CLK : INPUT;
N0 : INPUT;
N1 : INPUT;
N2 : INPUT;
N3 : INPUT;
N4 : INPUT;
N5 : INPUT;
N6 : INPUT;
N7 : INPUT;
PR_L : INPUT;
-- Node name is 'A'
-- Equation name is 'A', location is LC022, type is output.
A = LCELL( _EQ001 $ _EQ002);
_EQ001 = _LC023 & !_LC024 & !_LC029 & N4 & !N5 & !N6 & !N7 & _X001 &
_X002
# !_LC023 & !_LC024 & !_LC029 & N0 & !N1 & !N2 & !N3 & _X001 &
_X002
# _LC023 & !_LC024 & !_LC029 & N5 & N7 & _X001 & _X002
# _LC023 & !_LC024 & !_LC029 & !N4 & N6 & _X001 & _X002;
_X001 = EXP(!_LC023 & !_LC024 & !_LC029 & !N0 & N2);
_X002 = EXP(!_LC023 & !_LC024 & !_LC029 & N1 & N3);
_EQ002 = _X001 & _X002;
_X001 = EXP(!_LC023 & !_LC024 & !_LC029 & !N0 & N2);
_X002 = EXP(!_LC023 & !_LC024 & !_LC029 & N1 & N3);
-- Node name is 'B'
-- Equation name is 'B', location is LC030, type is output.
B = LCELL( _EQ003 $ _EQ004);
_EQ003 = _LC023 & !_LC024 & !_LC029 & !N4 & N5 & N6 & _X002 & _X003
# _LC023 & !_LC024 & !_LC029 & N4 & !N5 & N6 & _X002 & _X003
# !_LC023 & !_LC024 & !_LC029 & !N0 & N1 & N2 & _X002 & _X003
# !_LC023 & !_LC024 & !_LC029 & N0 & !N1 & N2 & _X002 & _X003;
_X002 = EXP(!_LC023 & !_LC024 & !_LC029 & N1 & N3);
_X003 = EXP( _LC023 & !_LC024 & !_LC029 & N5 & N7);
_EQ004 = _X002 & _X003;
_X002 = EXP(!_LC023 & !_LC024 & !_LC029 & N1 & N3);
_X003 = EXP( _LC023 & !_LC024 & !_LC029 & N5 & N7);
-- Node name is 'C'
-- Equation name is 'C', location is LC031, type is output.
C = LCELL( _EQ005 $ VCC);
_EQ005 = !_LC024 & !_LC029 & N2 & N3 & !N4 & N5 & N7
# _LC023 & !_LC024 & !_LC029 & !N4 & N5 & !N6
# !_LC023 & !_LC024 & !_LC029 & !N0 & N1 & !N2
# _LC023 & !_LC024 & !_LC029 & N6 & N7
# !_LC023 & !_LC024 & !_LC029 & N2 & N3;
-- Node name is 'D'
-- Equation name is 'D', location is LC032, type is output.
D = LCELL( _EQ006 $ _EQ007);
_EQ006 = _LC023 & !_LC024 & !_LC029 & N4 & N5 & N6 & _X004 & _X005
# !_LC023 & !_LC024 & !_LC029 & N0 & N1 & N2 & _X004 & _X005
# _LC023 & !_LC024 & !_LC029 & !N4 & !N5 & N6 & _X004 & _X005
# _LC023 & !_LC024 & !_LC029 & N4 & !N5 & !N6 & _X004 & _X005;
_X004 = EXP(!_LC023 & !_LC024 & !_LC029 & N0 & !N1 & !N2);
_X005 = EXP(!_LC023 & !_LC024 & !_LC029 & !N0 & !N1 & N2);
_EQ007 = _X004 & _X005;
_X004 = EXP(!_LC023 & !_LC024 & !_LC029 & N0 & !N1 & !N2);
_X005 = EXP(!_LC023 & !_LC024 & !_LC029 & !N0 & !N1 & N2);
-- Node name is 'E'
-- Equation name is 'E', location is LC026, type is output.
E = LCELL( _EQ008 $ VCC);
_EQ008 = _LC023 & !_LC024 & !_LC029 & !N5 & N6
# !_LC023 & !_LC024 & !_LC029 & !N1 & N2
# _LC023 & !_LC024 & !_LC029 & N4
# !_LC023 & !_LC024 & !_LC029 & N0;
-- Node name is 'F'
-- Equation name is 'F', location is LC027, type is output.
F = LCELL( _EQ009 $ VCC);
_EQ009 = _LC023 & !_LC024 & !_LC029 & N4 & !N6 & !N7
# !_LC023 & !_LC024 & !_LC029 & N0 & !N2 & !N3
# _LC023 & !_LC024 & !_LC029 & N5 & _X006
# !_LC023 & !_LC024 & !_LC029 & N1 & _X007;
_X006 = EXP(!N4 & N6);
_X007 = EXP(!N0 & N2);
-- Node name is 'G'
-- Equation name is 'G', location is LC028, type is output.
G = LCELL( _EQ010 $ _EQ011);
_EQ010 = _LC023 & !_LC024 & !_LC029 & N4 & N5 & N6
# !_LC023 & !_LC024 & !_LC029 & N0 & N1 & N2
# _LC023 & !_LC024 & !_LC029 & !N5 & !N6 & !N7
# !_LC023 & !_LC024 & !_LC029 & !N1 & !N2 & !N3;
_EQ011 = !_LC024 & !_LC029;
-- Node name is 'H'
-- Equation name is 'H', location is LC010, type is output.
H = LCELL( GND $ GND);
-- Node name is 'Y1'
-- Equation name is 'Y1', location is LC025, type is output.
Y1 = LCELL( _EQ012 $ GND);
_EQ012 = !_LC023 & !_LC024 & !_LC029;
-- Node name is 'Y2'
-- Equation name is 'Y2', location is LC017, type is output.
Y2 = LCELL( _EQ013 $ GND);
_EQ013 = _LC023 & !_LC024 & !_LC029;
-- Node name is 'Y3'
-- Equation name is 'Y3', location is LC018, type is output.
Y3 = LCELL( _EQ014 $ GND);
_EQ014 = !_LC023 & _LC024 & !_LC029;
-- Node name is 'Y4'
-- Equation name is 'Y4', location is LC019, type is output.
Y4 = LCELL( _EQ015 $ GND);
_EQ015 = _LC023 & _LC024 & !_LC029;
-- Node name is 'Y5'
-- Equation name is 'Y5', location is LC020, type is output.
Y5 = LCELL( _EQ016 $ GND);
_EQ016 = !_LC023 & !_LC024 & _LC029;
-- Node name is 'Y6'
-- Equation name is 'Y6', location is LC021, type is output.
Y6 = LCELL( _EQ017 $ GND);
_EQ017 = _LC023 & !_LC024 & _LC029;
-- Node name is '|05jishuqi:2|:1' = '|05jishuqi:2|Q1'
-- Equation name is '_LC023', type is buried
_LC023 = TFFE(!_EQ018, GLOBAL( CLK), VCC, PR_L, VCC);
_EQ018 = !_LC023 & _LC024 & _LC029;
-- Node name is '|05jishuqi:2|:2' = '|05jishuqi:2|Q2'
-- Equation name is '_LC024', type is buried
_LC024 = DFFE( _EQ019 $ GND, GLOBAL( CLK), VCC, PR_L, VCC);
_EQ019 = _LC023 & !_LC024 & !_LC029
# !_LC023 & _LC024 & !_LC029;
-- Node name is '|05jishuqi:2|:3' = '|05jishuqi:2|Q3'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE( _EQ020 $ GND, GLOBAL( CLK), VCC, PR_L, VCC);
_EQ020 = _LC023 & _LC024 & !_LC029
# !_LC023 & !_LC024 & _LC029;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\luogical experiment\the 8st\pinlvji\xianshi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 2,774K
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