📄 4santaimen.rpt
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-- synthesized logic cell
!_LC8_A8 = _LC8_A8~NOT;
_LC8_A8~NOT = LCELL( _EQ039);
_EQ039 = _LC2_A11 & !_LC5_A12
# !_LC6_A10;
-- Node name is '|4santai:40|~2~1~1~5'
-- Equation name is '_LC1_A8', type is buried
-- synthesized logic cell
!_LC1_A8 = _LC1_A8~NOT;
_LC1_A8~NOT = LCELL( _EQ040);
_EQ040 = _LC4_A11 & !_LC5_A8
# !_LC8_A8;
-- Node name is '|4santai:40|~2~1~1'
-- Equation name is '_LC2_A5', type is buried
!_LC2_A5 = _LC2_A5~NOT;
_LC2_A5~NOT = LCELL( _EQ041);
_EQ041 = !_LC6_A5 & !_LC6_A11
# !_LC1_A8;
-- Node name is '|4santai:40|~3~1~1~2'
-- Equation name is '_LC5_A3', type is buried
-- synthesized logic cell
_LC5_A3 = LCELL( _EQ042);
_EQ042 = !_LC2_A3 & !_LC6_A7
# !_LC4_A7 & !_LC8_A3;
-- Node name is '|4santai:40|~3~1~1~3'
-- Equation name is '_LC7_A12', type is buried
-- synthesized logic cell
_LC7_A12 = LCELL( _EQ043);
_EQ043 = !_LC1_A11 & !_LC4_A10
# _LC5_A3;
-- Node name is '|4santai:40|~3~1~1~4'
-- Equation name is '_LC3_A12', type is buried
-- synthesized logic cell
_LC3_A12 = LCELL( _EQ044);
_EQ044 = _LC2_A11 & !_LC6_A12
# _LC7_A12;
-- Node name is '|4santai:40|~3~1~1~5'
-- Equation name is '_LC2_A8', type is buried
-- synthesized logic cell
_LC2_A8 = LCELL( _EQ045);
_EQ045 = _LC4_A11 & !_LC7_A8
# _LC3_A12;
-- Node name is '|4santai:40|~3~1~1'
-- Equation name is '_LC3_A5', type is buried
!_LC3_A5 = _LC3_A5~NOT;
_LC3_A5~NOT = LCELL( _EQ046);
_EQ046 = !_LC6_A11 & !_LC8_A5
# _LC2_A8;
-- Node name is '|4santai:40|~4~1~1~2'
-- Equation name is '_LC1_A7', type is buried
-- synthesized logic cell
!_LC1_A7 = _LC1_A7~NOT;
_LC1_A7~NOT = LCELL( _EQ047);
_EQ047 = !_LC1_A10 & !_LC6_A7
# !_LC3_A3 & !_LC4_A7;
-- Node name is '|4santai:40|~4~1~1~3'
-- Equation name is '_LC2_A7', type is buried
-- synthesized logic cell
!_LC2_A7 = _LC2_A7~NOT;
_LC2_A7~NOT = LCELL( _EQ048);
_EQ048 = !_LC1_A11 & !_LC5_A10
# !_LC1_A7;
-- Node name is '|4santai:40|~4~1~1~4'
-- Equation name is '_LC3_A7', type is buried
-- synthesized logic cell
!_LC3_A7 = _LC3_A7~NOT;
_LC3_A7~NOT = LCELL( _EQ049);
_EQ049 = !_LC1_A12 & _LC2_A11
# !_LC2_A7;
-- Node name is '|4santai:40|~4~1~1~5'
-- Equation name is '_LC3_A11', type is buried
-- synthesized logic cell
!_LC3_A11 = _LC3_A11~NOT;
_LC3_A11~NOT = LCELL( _EQ050);
_EQ050 = !_LC4_A8 & _LC4_A11
# !_LC3_A7;
-- Node name is '|4santai:40|~4~1~1'
-- Equation name is '_LC4_A5', type is buried
!_LC4_A5 = _LC4_A5~NOT;
_LC4_A5~NOT = LCELL( _EQ051);
_EQ051 = !_LC5_A5 & !_LC6_A11
# !_LC3_A11;
-- Node name is '|05jishuqi:4|:1' = '|05jishuqi:4|Q1'
-- Equation name is '_LC5_A11', type is buried
_LC5_A11 = DFFE( _EQ052, CK, VCC, VCC, VCC);
_EQ052 = !_LC5_A11 & !_LC7_A11
# !_LC5_A11 & !_LC8_A11;
-- Node name is '|05jishuqi:4|:2' = '|05jishuqi:4|Q2'
-- Equation name is '_LC8_A11', type is buried
_LC8_A11 = DFFE( _EQ053, CK, VCC, VCC, VCC);
_EQ053 = _LC5_A11 & !_LC7_A11 & !_LC8_A11
# !_LC5_A11 & !_LC7_A11 & _LC8_A11;
-- Node name is '|05jishuqi:4|:3' = '|05jishuqi:4|Q3'
-- Equation name is '_LC7_A11', type is buried
_LC7_A11 = DFFE( _EQ054, CK, VCC, VCC, VCC);
_EQ054 = _LC2_A11
# _LC4_A11;
-- Node name is '|05jishuqi:4|:15'
-- Equation name is '_LC4_A11', type is buried
_LC4_A11 = LCELL( _EQ055);
_EQ055 = !_LC5_A11 & _LC7_A11 & !_LC8_A11;
-- Node name is '|05jishuqi:4|:16'
-- Equation name is '_LC2_A11', type is buried
_LC2_A11 = LCELL( _EQ056);
_EQ056 = _LC5_A11 & !_LC7_A11 & _LC8_A11;
-- Node name is '|7449:41|:34' = '|7449:41|OA'
-- Equation name is '_LC5_A14', type is buried
_LC5_A14 = LCELL( _EQ057);
_EQ057 = !_LC2_A5 & !_LC3_A5 & _LC4_A5
# !_LC1_A5 & !_LC2_A5 & !_LC3_A5
# _LC2_A5 & !_LC3_A5 & !_LC4_A5
# !_LC1_A5 & !_LC3_A5 & !_LC4_A5
# _LC1_A5 & !_LC2_A5 & _LC4_A5
# _LC1_A5 & !_LC2_A5 & _LC3_A5
# _LC1_A5 & _LC3_A5 & !_LC4_A5
# _LC1_A5 & _LC2_A5 & !_LC4_A5;
-- Node name is '|7449:41|:35' = '|7449:41|OB'
-- Equation name is '_LC1_A14', type is buried
_LC1_A14 = LCELL( _EQ058);
_EQ058 = !_LC1_A5 & !_LC2_A5
# !_LC2_A5 & !_LC3_A5
# _LC1_A5 & _LC2_A5 & !_LC4_A5
# !_LC3_A5 & !_LC4_A5;
-- Node name is '|7449:41|:31' = '|7449:41|OC'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = LCELL( _EQ059);
_EQ059 = !_LC2_A5 & !_LC4_A5
# _LC3_A5 & !_LC4_A5
# _LC1_A5 & !_LC4_A5
# !_LC2_A5 & !_LC3_A5
# _LC1_A5 & !_LC3_A5;
-- Node name is '|7449:41|:36' = '|7449:41|OD'
-- Equation name is '_LC4_A15', type is buried
_LC4_A15 = LCELL( _EQ060);
_EQ060 = _LC2_A5 & !_LC3_A5
# _LC1_A5 & !_LC2_A5 & _LC3_A5
# !_LC1_A5 & _LC2_A5
# !_LC1_A5 & !_LC3_A5;
-- Node name is '|7449:41|:32' = '|7449:41|OE'
-- Equation name is '_LC6_A18', type is buried
_LC6_A18 = LCELL( _EQ061);
_EQ061 = !_LC1_A5 & _LC2_A5
# !_LC1_A5 & !_LC3_A5;
-- Node name is '|7449:41|:37' = '|7449:41|OF'
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = LCELL( _EQ062);
_EQ062 = !_LC2_A5 & _LC4_A5
# !_LC2_A5 & _LC3_A5
# !_LC1_A5 & !_LC2_A5
# !_LC1_A5 & _LC3_A5;
-- Node name is '|7449:41|:33' = '|7449:41|OG'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = LCELL( _EQ063);
_EQ063 = !_LC2_A5 & _LC4_A5
# !_LC3_A5 & _LC4_A5
# !_LC1_A5 & _LC4_A5
# !_LC2_A5 & _LC3_A5
# !_LC1_A5 & _LC3_A5
# _LC2_A5 & !_LC3_A5
# !_LC1_A5 & _LC2_A5;
-- Node name is '|74138:6|:15' = '|74138:6|Y0N'
-- Equation name is '_LC4_A7', type is buried
_LC4_A7 = LCELL( _EQ064);
_EQ064 = _LC5_A11
# _LC8_A11
# _LC7_A11;
-- Node name is '|74138:6|:16' = '|74138:6|Y1N'
-- Equation name is '_LC6_A7', type is buried
_LC6_A7 = LCELL( _EQ065);
_EQ065 = !_LC5_A11
# _LC8_A11
# _LC7_A11;
-- Node name is '|74138:6|:17' = '|74138:6|Y2N'
-- Equation name is '_LC1_A11', type is buried
_LC1_A11 = LCELL( _EQ066);
_EQ066 = _LC7_A11
# !_LC8_A11
# _LC5_A11;
-- Node name is '|74138:6|:20' = '|74138:6|Y5N'
-- Equation name is '_LC6_A11', type is buried
_LC6_A11 = LCELL( _EQ067);
_EQ067 = !_LC5_A11
# _LC8_A11
# !_LC7_A11;
Project Information d:\luogical experiment\the 8st\pinlvji\4santaimen.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:04
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:09
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,728K
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