📄 4santaimen.rpt
字号:
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\4santaimen.rpt
4santaimen
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 2/22( 9%)
A3 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 1/2 6/22( 27%)
A5 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
A7 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A8 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
A10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 1/2 8/22( 36%)
A11 8/ 8(100%) 4/ 8( 50%) 8/ 8(100%) 1/2 0/2 3/22( 13%)
A12 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 8/22( 36%)
A14 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A15 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A18 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 16/96 ( 16%)
Total logic cells used: 67/1152 ( 5%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.41/4 ( 85%)
Total fan-in: 229/4608 ( 4%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 14
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 67
Total flipflops required: 31
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 16/1152 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 7 0 8 0 8 0 5 8 0 8 8 8 0 0 2 2 0 0 3 0 0 0 0 0 0 67/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 7 0 8 0 8 0 5 8 0 8 8 8 0 0 2 2 0 0 3 0 0 0 0 0 0 67/0
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\4santaimen.rpt
4santaimen
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
128 - - - 13 INPUT 0 0 0 3 CK
122 - - - 13 INPUT 0 0 0 4 CKL
125 - - - -- INPUT 0 0 0 1 CP
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\4santaimen.rpt
4santaimen
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
51 - - - 14 OUTPUT 0 1 0 0 a
49 - - - 14 OUTPUT 0 1 0 0 b
48 - - - 15 OUTPUT 0 1 0 0 c
47 - - - 16 OUTPUT 0 1 0 0 d
46 - - - 17 OUTPUT 0 1 0 0 e
44 - - - 18 OUTPUT 0 1 0 0 f
43 - - - 18 OUTPUT 0 1 0 0 g
42 - - - 19 OUTPUT 0 0 0 0 H
101 - - A -- OUTPUT 0 1 0 0 Y0
100 - - A -- OUTPUT 0 1 0 0 Y1
99 - - B -- OUTPUT 0 1 0 0 Y2
98 - - B -- OUTPUT 0 1 0 0 Y3
97 - - B -- OUTPUT 0 1 0 0 Y4
96 - - B -- OUTPUT 0 1 0 0 Y5
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\4santaimen.rpt
4santaimen
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 03 DFFE 0 5 0 8 |jishuqi:3|09jishuqi:4|Q3 (|jishuqi:3|09jishuqi:4|:12)
- 8 - A 03 DFFE 0 5 0 3 |jishuqi:3|09jishuqi:4|Q2 (|jishuqi:3|09jishuqi:4|:13)
- 6 - A 03 DFFE 0 4 0 4 |jishuqi:3|09jishuqi:4|Q1 (|jishuqi:3|09jishuqi:4|:14)
- 7 - A 03 DFFE 0 5 0 4 |jishuqi:3|09jishuqi:4|Q0 (|jishuqi:3|09jishuqi:4|:15)
- 5 - A 10 DFFE 0 5 0 8 |jishuqi:3|09jishuqi:5|Q3 (|jishuqi:3|09jishuqi:5|:12)
- 4 - A 10 DFFE 0 5 0 3 |jishuqi:3|09jishuqi:5|Q2 (|jishuqi:3|09jishuqi:5|:13)
- 7 - A 10 DFFE 0 4 0 4 |jishuqi:3|09jishuqi:5|Q1 (|jishuqi:3|09jishuqi:5|:14)
- 3 - A 10 DFFE 0 5 0 4 |jishuqi:3|09jishuqi:5|Q0 (|jishuqi:3|09jishuqi:5|:15)
- 1 - A 10 DFFE 0 5 0 8 |jishuqi:3|09jishuqi:6|Q3 (|jishuqi:3|09jishuqi:6|:12)
- 2 - A 03 DFFE 0 5 0 3 |jishuqi:3|09jishuqi:6|Q2 (|jishuqi:3|09jishuqi:6|:13)
- 2 - A 10 DFFE 0 4 0 4 |jishuqi:3|09jishuqi:6|Q1 (|jishuqi:3|09jishuqi:6|:14)
- 1 - A 03 DFFE 0 5 0 4 |jishuqi:3|09jishuqi:6|Q0 (|jishuqi:3|09jishuqi:6|:15)
- 4 - A 08 DFFE 0 5 0 8 |jishuqi:3|09jishuqi:7|Q3 (|jishuqi:3|09jishuqi:7|:12)
- 7 - A 08 DFFE 0 5 0 3 |jishuqi:3|09jishuqi:7|Q2 (|jishuqi:3|09jishuqi:7|:13)
- 5 - A 08 DFFE 0 4 0 4 |jishuqi:3|09jishuqi:7|Q1 (|jishuqi:3|09jishuqi:7|:14)
- 6 - A 08 DFFE 0 5 0 4 |jishuqi:3|09jishuqi:7|Q0 (|jishuqi:3|09jishuqi:7|:15)
- 5 - A 05 DFFE 0 5 0 4 |jishuqi:3|09jishuqi:8|Q3 (|jishuqi:3|09jishuqi:8|:12)
- 8 - A 05 DFFE 0 5 0 3 |jishuqi:3|09jishuqi:8|Q2 (|jishuqi:3|09jishuqi:8|:13)
- 6 - A 05 DFFE 0 4 0 4 |jishuqi:3|09jishuqi:8|Q1 (|jishuqi:3|09jishuqi:8|:14)
- 7 - A 05 DFFE 0 5 0 4 |jishuqi:3|09jishuqi:8|Q0 (|jishuqi:3|09jishuqi:8|:15)
- 1 - A 12 DFFE 0 5 0 8 |jishuqi:3|09jishuqi:9|Q3 (|jishuqi:3|09jishuqi:9|:12)
- 6 - A 12 DFFE 0 5 0 3 |jishuqi:3|09jishuqi:9|Q2 (|jishuqi:3|09jishuqi:9|:13)
- 5 - A 12 DFFE 0 4 0 4 |jishuqi:3|09jishuqi:9|Q1 (|jishuqi:3|09jishuqi:9|:14)
- 4 - A 12 DFFE 0 5 0 4 |jishuqi:3|09jishuqi:9|Q0 (|jishuqi:3|09jishuqi:9|:15)
- 2 - A 01 AND2 1 2 0 4 |jishuqi:3|7408:14|1 (|jishuqi:3|7408:14|:4)
- 1 - A 01 OR2 ! 0 4 0 24 |kongzhidianlu:2|ENCLR (|kongzhidianlu:2|:6)
- 4 - A 01 DFFE 1 3 0 5 |kongzhidianlu:2|08jishuqi:1|Q3 (|kongzhidianlu:2|08jishuqi:1|:12)
- 5 - A 01 DFFE 1 3 0 3 |kongzhidianlu:2|08jishuqi:1|Q2 (|kongzhidianlu:2|08jishuqi:1|:13)
- 7 - A 01 DFFE 1 2 0 4 |kongzhidianlu:2|08jishuqi:1|Q1 (|kongzhidianlu:2|08jishuqi:1|:14)
- 6 - A 01 DFFE 1 1 0 5 |kongzhidianlu:2|08jishuqi:1|Q0 (|kongzhidianlu:2|08jishuqi:1|:15)
- 3 - A 01 OR2 0 3 0 1 |kongzhidianlu:2|08jishuqi:1|7408:22|1 (|kongzhidianlu:2|08jishuqi:1|7408:22|:4)
- 4 - A 03 OR2 s ! 0 4 0 1 |4santai:40|~1~1~1~2
- 8 - A 12 OR2 s ! 0 3 0 1 |4santai:40|~1~1~1~3
- 2 - A 12 OR2 s ! 0 3 0 1 |4santai:40|~1~1~1~4
- 3 - A 08 OR2 s ! 0 3 0 1 |4santai:40|~1~1~1~5
- 1 - A 05 OR2 0 3 0 7 |4santai:40|~1~1~1
- 8 - A 10 OR2 s ! 0 4 0 1 |4santai:40|~2~1~1~2
- 6 - A 10 OR2 s ! 0 3 0 1 |4santai:40|~2~1~1~3
- 8 - A 08 OR2 s ! 0 3 0 1 |4santai:40|~2~1~1~4
- 1 - A 08 OR2 s ! 0 3 0 1 |4santai:40|~2~1~1~5
- 2 - A 05 OR2 ! 0 3 0 7 |4santai:40|~2~1~1
- 5 - A 03 OR2 s 0 4 0 1 |4santai:40|~3~1~1~2
- 7 - A 12 OR2 s 0 3 0 1 |4santai:40|~3~1~1~3
- 3 - A 12 OR2 s 0 3 0 1 |4santai:40|~3~1~1~4
- 2 - A 08 OR2 s 0 3 0 1 |4santai:40|~3~1~1~5
- 3 - A 05 OR2 ! 0 3 0 7 |4santai:40|~3~1~1
- 1 - A 07 OR2 s ! 0 4 0 1 |4santai:40|~4~1~1~2
- 2 - A 07 OR2 s ! 0 3 0 1 |4santai:40|~4~1~1~3
- 3 - A 07 OR2 s ! 0 3 0 1 |4santai:40|~4~1~1~4
- 3 - A 11 OR2 s ! 0 3 0 1 |4santai:40|~4~1~1~5
- 4 - A 05 OR2 ! 0 3 0 5 |4santai:40|~4~1~1
- 5 - A 11 DFFE 1 2 0 7 |05jishuqi:4|Q1 (|05jishuqi:4|:1)
- 8 - A 11 DFFE 1 2 0 7 |05jishuqi:4|Q2 (|05jishuqi:4|:2)
- 7 - A 11 DFFE 1 2 0 8 |05jishuqi:4|Q3 (|05jishuqi:4|:3)
- 4 - A 11 AND2 0 3 1 5 |05jishuqi:4|:15
- 2 - A 11 AND2 0 3 1 5 |05jishuqi:4|:16
- 1 - A 15 OR2 0 4 1 0 |7449:41|OC (|7449:41|:31)
- 6 - A 18 OR2 0 3 1 0 |7449:41|OE (|7449:41|:32)
- 1 - A 18 OR2 0 4 1 0 |7449:41|OG (|7449:41|:33)
- 5 - A 14 OR2 0 4 1 0 |7449:41|OA (|7449:41|:34)
- 1 - A 14 OR2 0 4 1 0 |7449:41|OB (|7449:41|:35)
- 4 - A 15 OR2 0 3 1 0 |7449:41|OD (|7449:41|:36)
- 5 - A 18 OR2 0 4 1 0 |7449:41|OF (|7449:41|:37)
- 4 - A 07 OR2 0 3 1 4 |74138:6|Y0N (|74138:6|:15)
- 6 - A 07 OR2 0 3 1 4 |74138:6|Y1N (|74138:6|:16)
- 1 - A 11 OR2 0 3 1 4 |74138:6|Y2N (|74138:6|:17)
- 6 - A 11 OR2 0 3 1 4 |74138:6|Y5N (|74138:6|:20)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\4santaimen.rpt
4santaimen
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 10/ 96( 10%) 29/ 48( 60%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\4santaimen.rpt
4santaimen
** CLOCK SIGNALS **
Type Fan-out Name
DFF 9 |jishuqi:3|09jishuqi:4|Q3
DFF 9 |jishuqi:3|09jishuqi:5|Q3
DFF 9 |jishuqi:3|09jishuqi:6|Q3
DFF 9 |jishuqi:3|09jishuqi:7|Q3
DFF 9 |jishuqi:3|09jishuqi:9|Q3
INPUT 4 CKL
LCELL 4 |jishuqi:3|7408:14|1
INPUT 3 CK
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\4santaimen.rpt
4santaimen
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 24 |kongzhidianlu:2|ENCLR
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\4santaimen.rpt
4santaimen
** EQUATIONS **
CK : INPUT;
CKL : INPUT;
CP : INPUT;
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