📄 05jishuqi.rpt
字号:
66 - - B -- OUTPUT 0 1 0 0 Q1
64 - - B -- OUTPUT 0 1 0 0 Q2
67 - - B -- OUTPUT 0 1 0 0 Q3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:k:\luogical experiment\the 8st\pinlvji\05jishuqi.rpt
05jishuqi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 17 DFFE + 0 2 1 2 :1
- 7 - B 17 DFFE + 0 2 1 2 :2
- 1 - B 17 DFFE + 0 2 1 2 :3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:k:\luogical experiment\the 8st\pinlvji\05jishuqi.rpt
05jishuqi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:k:\luogical experiment\the 8st\pinlvji\05jishuqi.rpt
05jishuqi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 CLK
Device-Specific Information:k:\luogical experiment\the 8st\pinlvji\05jishuqi.rpt
05jishuqi
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 3 CLR_L
Device-Specific Information:k:\luogical experiment\the 8st\pinlvji\05jishuqi.rpt
05jishuqi
** EQUATIONS **
CLK : INPUT;
CLR_L : INPUT;
PR_L : INPUT;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC3_B17;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC7_B17;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC1_B17;
-- Node name is ':1'
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = DFFE( _EQ001, GLOBAL( CLK), GLOBAL( CLR_L), GLOBAL( PR_L), VCC);
_EQ001 = !_LC3_B17 & !_LC7_B17
# !_LC1_B17 & !_LC3_B17;
-- Node name is ':2'
-- Equation name is '_LC7_B17', type is buried
_LC7_B17 = DFFE( _EQ002, GLOBAL( CLK), GLOBAL( CLR_L), GLOBAL( PR_L), VCC);
_EQ002 = !_LC1_B17 & _LC3_B17 & !_LC7_B17
# !_LC1_B17 & !_LC3_B17 & _LC7_B17;
-- Node name is ':3'
-- Equation name is '_LC1_B17', type is buried
_LC1_B17 = DFFE( _EQ003, GLOBAL( CLK), GLOBAL( CLR_L), GLOBAL( PR_L), VCC);
_EQ003 = _LC1_B17 & !_LC3_B17 & !_LC7_B17
# !_LC1_B17 & _LC3_B17 & _LC7_B17;
Project Information k:\luogical experiment\the 8st\pinlvji\05jishuqi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:25
Timing SNF Extractor 00:00:01
Assembler 00:00:11
-------------------------- --------
Total Time 00:00:40
Memory Allocated
-----------------
Peak memory allocated during compilation = 12,962K
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