pinlvji.rpt

在max_plus2和FPGA实验箱上实现频率计的功能

-- Node name is '|xianshidianlu:2|4santai:98|~2~1~1~4' 
-- Equation name is '_LC8_B19', type is buried 
-- synthesized logic cell 
!_LC8_B19 = _LC8_B19~NOT;
_LC8_B19~NOT = LCELL( _EQ039);
  _EQ039 =  _LC2_B4 & !_LC5_B15
         # !_LC7_B22;

-- Node name is '|xianshidianlu:2|4santai:98|~2~1~1~5' 
-- Equation name is '_LC2_B19', type is buried 
-- synthesized logic cell 
!_LC2_B19 = _LC2_B19~NOT;
_LC2_B19~NOT = LCELL( _EQ040);
  _EQ040 =  _LC3_B4 & !_LC5_B19
         # !_LC8_B19;

-- Node name is '|xianshidianlu:2|4santai:98|~2~1~1' 
-- Equation name is '_LC3_B21', type is buried 
!_LC3_B21 = _LC3_B21~NOT;
_LC3_B21~NOT = LCELL( _EQ041);
  _EQ041 = !_LC5_B4 & !_LC6_B21
         # !_LC2_B19;

-- Node name is '|xianshidianlu:2|4santai:98|~3~1~1~2' 
-- Equation name is '_LC1_B20', type is buried 
-- synthesized logic cell 
_LC1_B20 = LCELL( _EQ042);
  _EQ042 = !_LC6_B2 & !_LC6_B22
         # !_LC4_B2 & !_LC7_B20;

-- Node name is '|xianshidianlu:2|4santai:98|~3~1~1~3' 
-- Equation name is '_LC6_B15', type is buried 
-- synthesized logic cell 
_LC6_B15 = LCELL( _EQ043);
  _EQ043 = !_LC1_B4 & !_LC5_B22
         #  _LC1_B20;

-- Node name is '|xianshidianlu:2|4santai:98|~3~1~1~4' 
-- Equation name is '_LC3_B15', type is buried 
-- synthesized logic cell 
_LC3_B15 = LCELL( _EQ044);
  _EQ044 =  _LC2_B4 & !_LC4_B15
         #  _LC6_B15;

-- Node name is '|xianshidianlu:2|4santai:98|~3~1~1~5' 
-- Equation name is '_LC4_B19', type is buried 
-- synthesized logic cell 
_LC4_B19 = LCELL( _EQ045);
  _EQ045 =  _LC3_B4 & !_LC7_B19
         #  _LC3_B15;

-- Node name is '|xianshidianlu:2|4santai:98|~3~1~1' 
-- Equation name is '_LC2_B21', type is buried 
!_LC2_B21 = _LC2_B21~NOT;
_LC2_B21~NOT = LCELL( _EQ046);
  _EQ046 = !_LC5_B4 & !_LC8_B21
         #  _LC4_B19;

-- Node name is '|xianshidianlu:2|4santai:98|~4~1~1~2' 
-- Equation name is '_LC2_B2', type is buried 
-- synthesized logic cell 
!_LC2_B2 = _LC2_B2~NOT;
_LC2_B2~NOT = LCELL( _EQ047);
  _EQ047 = !_LC1_B22 & !_LC6_B2
         # !_LC4_B2 & !_LC6_B20;

-- Node name is '|xianshidianlu:2|4santai:98|~4~1~1~3' 
-- Equation name is '_LC3_B2', type is buried 
-- synthesized logic cell 
!_LC3_B2 = _LC3_B2~NOT;
_LC3_B2~NOT = LCELL( _EQ048);
  _EQ048 = !_LC1_B4 & !_LC4_B22
         # !_LC2_B2;

-- Node name is '|xianshidianlu:2|4santai:98|~4~1~1~4' 
-- Equation name is '_LC1_B2', type is buried 
-- synthesized logic cell 
!_LC1_B2 = _LC1_B2~NOT;
_LC1_B2~NOT = LCELL( _EQ049);
  _EQ049 =  _LC2_B4 & !_LC8_B15
         # !_LC3_B2;

-- Node name is '|xianshidianlu:2|4santai:98|~4~1~1~5' 
-- Equation name is '_LC4_B4', type is buried 
-- synthesized logic cell 
!_LC4_B4 = _LC4_B4~NOT;
_LC4_B4~NOT = LCELL( _EQ050);
  _EQ050 =  _LC3_B4 & !_LC3_B19
         # !_LC1_B2;

-- Node name is '|xianshidianlu:2|4santai:98|~4~1~1' 
-- Equation name is '_LC4_B21', type is buried 
!_LC4_B21 = _LC4_B21~NOT;
_LC4_B21~NOT = LCELL( _EQ051);
  _EQ051 = !_LC5_B4 & !_LC5_B21
         # !_LC4_B4;

-- Node name is '|xianshidianlu:2|05jishuqi:46|:1' = '|xianshidianlu:2|05jishuqi:46|Q1' 
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = DFFE( _EQ052,  CK,  VCC,  VCC,  VCC);
  _EQ052 = !_LC6_B4 & !_LC7_B4
         # !_LC6_B4 & !_LC8_B4;

-- Node name is '|xianshidianlu:2|05jishuqi:46|:2' = '|xianshidianlu:2|05jishuqi:46|Q2' 
-- Equation name is '_LC7_B4', type is buried 
_LC7_B4  = DFFE( _EQ053,  CK,  VCC,  VCC,  VCC);
  _EQ053 =  _LC6_B4 & !_LC7_B4 & !_LC8_B4
         # !_LC6_B4 &  _LC7_B4 & !_LC8_B4;

-- Node name is '|xianshidianlu:2|05jishuqi:46|:3' = '|xianshidianlu:2|05jishuqi:46|Q3' 
-- Equation name is '_LC8_B4', type is buried 
_LC8_B4  = DFFE( _EQ054,  CK,  VCC,  VCC,  VCC);
  _EQ054 =  _LC2_B4
         #  _LC3_B4;

-- Node name is '|xianshidianlu:2|05jishuqi:46|:15' 
-- Equation name is '_LC3_B4', type is buried 
_LC3_B4  = LCELL( _EQ055);
  _EQ055 = !_LC6_B4 & !_LC7_B4 &  _LC8_B4;

-- Node name is '|xianshidianlu:2|05jishuqi:46|:16' 
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = LCELL( _EQ056);
  _EQ056 =  _LC6_B4 &  _LC7_B4 & !_LC8_B4;

-- Node name is '|xianshidianlu:2|7449:18|:34' = '|xianshidianlu:2|7449:18|OA' 
-- Equation name is '_LC3_B14', type is buried 
_LC3_B14 = LCELL( _EQ057);
  _EQ057 = !_LC2_B21 & !_LC3_B21 &  _LC4_B21
         # !_LC1_B21 & !_LC2_B21 & !_LC3_B21
         # !_LC2_B21 &  _LC3_B21 & !_LC4_B21
         # !_LC1_B21 & !_LC2_B21 & !_LC4_B21
         #  _LC1_B21 & !_LC3_B21 &  _LC4_B21
         #  _LC1_B21 &  _LC2_B21 & !_LC3_B21
         #  _LC1_B21 &  _LC2_B21 & !_LC4_B21
         #  _LC1_B21 &  _LC3_B21 & !_LC4_B21;

-- Node name is '|xianshidianlu:2|7449:18|:35' = '|xianshidianlu:2|7449:18|OB' 
-- Equation name is '_LC2_B14', type is buried 
_LC2_B14 = LCELL( _EQ058);
  _EQ058 = !_LC1_B21 & !_LC3_B21
         # !_LC2_B21 & !_LC3_B21
         #  _LC1_B21 &  _LC3_B21 & !_LC4_B21
         # !_LC2_B21 & !_LC4_B21;

-- Node name is '|xianshidianlu:2|7449:18|:31' = '|xianshidianlu:2|7449:18|OC' 
-- Equation name is '_LC4_B16', type is buried 
_LC4_B16 = LCELL( _EQ059);
  _EQ059 = !_LC3_B21 & !_LC4_B21
         #  _LC2_B21 & !_LC4_B21
         #  _LC1_B21 & !_LC4_B21
         # !_LC2_B21 & !_LC3_B21
         #  _LC1_B21 & !_LC2_B21;

-- Node name is '|xianshidianlu:2|7449:18|:36' = '|xianshidianlu:2|7449:18|OD' 
-- Equation name is '_LC3_B16', type is buried 
_LC3_B16 = LCELL( _EQ060);
  _EQ060 = !_LC2_B21 &  _LC3_B21
         #  _LC1_B21 &  _LC2_B21 & !_LC3_B21
         # !_LC1_B21 &  _LC3_B21
         # !_LC1_B21 & !_LC2_B21;

-- Node name is '|xianshidianlu:2|7449:18|:32' = '|xianshidianlu:2|7449:18|OE' 
-- Equation name is '_LC4_B18', type is buried 
_LC4_B18 = LCELL( _EQ061);
  _EQ061 = !_LC1_B21 &  _LC3_B21
         # !_LC1_B21 & !_LC2_B21;

-- Node name is '|xianshidianlu:2|7449:18|:37' = '|xianshidianlu:2|7449:18|OF' 
-- Equation name is '_LC5_B18', type is buried 
_LC5_B18 = LCELL( _EQ062);
  _EQ062 = !_LC3_B21 &  _LC4_B21
         #  _LC2_B21 & !_LC3_B21
         # !_LC1_B21 & !_LC3_B21
         # !_LC1_B21 &  _LC2_B21;

-- Node name is '|xianshidianlu:2|7449:18|:33' = '|xianshidianlu:2|7449:18|OG' 
-- Equation name is '_LC1_B18', type is buried 
_LC1_B18 = LCELL( _EQ063);
  _EQ063 = !_LC3_B21 &  _LC4_B21
         # !_LC2_B21 &  _LC4_B21
         # !_LC1_B21 &  _LC4_B21
         #  _LC2_B21 & !_LC3_B21
         # !_LC1_B21 &  _LC2_B21
         # !_LC2_B21 &  _LC3_B21
         # !_LC1_B21 &  _LC3_B21;

-- Node name is '|xianshidianlu:2|74138:76|:15' = '|xianshidianlu:2|74138:76|Y0N' 
-- Equation name is '_LC4_B2', type is buried 
_LC4_B2  = LCELL( _EQ064);
  _EQ064 =  _LC6_B4
         #  _LC8_B4
         #  _LC7_B4;

-- Node name is '|xianshidianlu:2|74138:76|:16' = '|xianshidianlu:2|74138:76|Y1N' 
-- Equation name is '_LC6_B2', type is buried 
!_LC6_B2 = _LC6_B2~NOT;
_LC6_B2~NOT = LCELL( _EQ065);
  _EQ065 =  _LC6_B4 & !_LC7_B4 & !_LC8_B4;

-- Node name is '|xianshidianlu:2|74138:76|:17' = '|xianshidianlu:2|74138:76|Y2N' 
-- Equation name is '_LC1_B4', type is buried 
!_LC1_B4 = _LC1_B4~NOT;
_LC1_B4~NOT = LCELL( _EQ066);
  _EQ066 = !_LC6_B4 &  _LC7_B4 & !_LC8_B4;

-- Node name is '|xianshidianlu:2|74138:76|:20' = '|xianshidianlu:2|74138:76|Y5N' 
-- Equation name is '_LC5_B4', type is buried 
!_LC5_B4 = _LC5_B4~NOT;
_LC5_B4~NOT = LCELL( _EQ067);
  _EQ067 =  _LC6_B4 & !_LC7_B4 &  _LC8_B4;



Project Information        f:\luogical  experiment\the 8st\pinlvji\pinlvji.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:01
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,887K