📄 xianshidianlu.rpt
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-- Node name is '|4santai:98|~2~1~1'
-- Equation name is '_LC1_B24', type is buried
!_LC1_B24 = _LC1_B24~NOT;
_LC1_B24~NOT = LCELL( _EQ008);
_EQ008 = !_LC6_B14 & !N1
# _LC7_B24
# _LC8_B24;
-- Node name is '|4santai:98|~3~1~1~2'
-- Equation name is '_LC5_B19', type is buried
-- synthesized logic cell
!_LC5_B19 = _LC5_B19~NOT;
_LC5_B19~NOT = LCELL( _EQ009);
_EQ009 = _LC8_B14 & !N18
# _LC4_B14 & !N14;
-- Node name is '|4santai:98|~3~1~1~3'
-- Equation name is '_LC6_B19', type is buried
-- synthesized logic cell
!_LC6_B19 = _LC6_B19~NOT;
_LC6_B19~NOT = LCELL( _EQ010);
_EQ010 = !_LC2_B14 & !N22
# !_LC5_B19;
-- Node name is '|4santai:98|~3~1~1~4'
-- Equation name is '_LC7_B19', type is buried
-- synthesized logic cell
!_LC7_B19 = _LC7_B19~NOT;
_LC7_B19~NOT = LCELL( _EQ011);
_EQ011 = !_LC1_B14 & !N10
# !_LC5_B14 & !N6;
-- Node name is '|4santai:98|~3~1~1'
-- Equation name is '_LC1_B19', type is buried
!_LC1_B19 = _LC1_B19~NOT;
_LC1_B19~NOT = LCELL( _EQ012);
_EQ012 = !_LC6_B14 & !N2
# !_LC6_B19
# !_LC7_B19;
-- Node name is '|4santai:98|~4~1~1~2'
-- Equation name is '_LC3_B24', type is buried
-- synthesized logic cell
!_LC3_B24 = _LC3_B24~NOT;
_LC3_B24~NOT = LCELL( _EQ013);
_EQ013 = _LC8_B14 & !N19
# _LC4_B14 & !N15;
-- Node name is '|4santai:98|~4~1~1~3'
-- Equation name is '_LC4_B24', type is buried
-- synthesized logic cell
!_LC4_B24 = _LC4_B24~NOT;
_LC4_B24~NOT = LCELL( _EQ014);
_EQ014 = !_LC2_B14 & !N23
# !_LC3_B24;
-- Node name is '|4santai:98|~4~1~1~4'
-- Equation name is '_LC5_B24', type is buried
-- synthesized logic cell
!_LC5_B24 = _LC5_B24~NOT;
_LC5_B24~NOT = LCELL( _EQ015);
_EQ015 = !_LC1_B14 & !N11
# !_LC5_B14 & !N7;
-- Node name is '|4santai:98|~4~1~1'
-- Equation name is '_LC2_B24', type is buried
!_LC2_B24 = _LC2_B24~NOT;
_LC2_B24~NOT = LCELL( _EQ016);
_EQ016 = !_LC6_B14 & !N3
# !_LC4_B24
# !_LC5_B24;
-- Node name is '|05jishuqi:46|:1' = '|05jishuqi:46|Q1'
-- Equation name is '_LC3_B14', type is buried
!_LC3_B14 = _LC3_B14~NOT;
_LC3_B14~NOT = DFFE( _EQ017, GLOBAL( CLK), GLOBAL( PR_L), VCC, VCC);
_EQ017 = _LC3_B14
# _LC7_B14 & _LC8_B19;
-- Node name is '|05jishuqi:46|:2' = '|05jishuqi:46|Q2'
-- Equation name is '_LC7_B14', type is buried
!_LC7_B14 = _LC7_B14~NOT;
_LC7_B14~NOT = DFFE( _EQ018, GLOBAL( CLK), GLOBAL( PR_L), VCC, VCC);
_EQ018 = _LC3_B14 & _LC7_B14
# !_LC3_B14 & !_LC7_B14
# _LC8_B19;
-- Node name is '|05jishuqi:46|:3' = '|05jishuqi:46|Q3'
-- Equation name is '_LC8_B19', type is buried
!_LC8_B19 = _LC8_B19~NOT;
_LC8_B19~NOT = DFFE( _EQ019, GLOBAL( CLK), GLOBAL( PR_L), VCC, VCC);
_EQ019 = !_LC4_B14 & !_LC8_B14;
-- Node name is '|05jishuqi:46|:15'
-- Equation name is '_LC8_B14', type is buried
!_LC8_B14 = _LC8_B14~NOT;
_LC8_B14~NOT = LCELL( _EQ020);
_EQ020 = _LC3_B14
# _LC7_B14
# !_LC8_B19;
-- Node name is '|05jishuqi:46|:16'
-- Equation name is '_LC4_B14', type is buried
!_LC4_B14 = _LC4_B14~NOT;
_LC4_B14~NOT = LCELL( _EQ021);
_EQ021 = !_LC3_B14
# !_LC7_B14
# _LC8_B19;
-- Node name is '|7449:18|:34' = '|7449:18|OA'
-- Equation name is '_LC4_B20', type is buried
_LC4_B20 = LCELL( _EQ022);
_EQ022 = _LC1_B24 & !_LC2_B24 & _LC7_B20
# _LC1_B19 & !_LC2_B24 & _LC7_B20
# _LC1_B19 & !_LC1_B24 & _LC7_B20
# !_LC1_B24 & _LC2_B24 & _LC7_B20
# !_LC1_B19 & _LC1_B24 & !_LC2_B24
# !_LC1_B19 & !_LC2_B24 & !_LC7_B20
# !_LC1_B19 & !_LC1_B24 & !_LC7_B20
# !_LC1_B19 & !_LC1_B24 & _LC2_B24;
-- Node name is '|7449:18|:35' = '|7449:18|OB'
-- Equation name is '_LC6_B20', type is buried
_LC6_B20 = LCELL( _EQ023);
_EQ023 = !_LC1_B24 & !_LC7_B20
# _LC1_B24 & !_LC2_B24 & _LC7_B20
# !_LC1_B19 & !_LC2_B24
# !_LC1_B19 & !_LC1_B24;
-- Node name is '|7449:18|:31' = '|7449:18|OC'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = LCELL( _EQ024);
_EQ024 = !_LC1_B24 & !_LC2_B24
# !_LC1_B19 & !_LC1_B24
# !_LC2_B24 & _LC7_B20
# !_LC1_B19 & _LC7_B20
# _LC1_B19 & !_LC2_B24;
-- Node name is '|7449:18|:36' = '|7449:18|OD'
-- Equation name is '_LC3_B20', type is buried
_LC3_B20 = LCELL( _EQ025);
_EQ025 = _LC1_B24 & !_LC7_B20
# !_LC1_B19 & _LC1_B24
# _LC1_B19 & !_LC1_B24 & _LC7_B20
# !_LC1_B19 & !_LC7_B20;
-- Node name is '|7449:18|:32' = '|7449:18|OE'
-- Equation name is '_LC1_B20', type is buried
_LC1_B20 = LCELL( _EQ026);
_EQ026 = _LC1_B24 & !_LC7_B20
# !_LC1_B19 & !_LC7_B20;
-- Node name is '|7449:18|:37' = '|7449:18|OF'
-- Equation name is '_LC5_B20', type is buried
_LC5_B20 = LCELL( _EQ027);
_EQ027 = !_LC1_B24 & _LC2_B24
# !_LC1_B24 & !_LC7_B20
# _LC1_B19 & !_LC1_B24
# _LC1_B19 & !_LC7_B20;
-- Node name is '|7449:18|:33' = '|7449:18|OG'
-- Equation name is '_LC8_B20', type is buried
_LC8_B20 = LCELL( _EQ028);
_EQ028 = _LC1_B19 & !_LC1_B24
# !_LC1_B24 & _LC2_B24
# _LC1_B24 & !_LC7_B20
# _LC1_B19 & !_LC7_B20
# _LC2_B24 & !_LC7_B20
# !_LC1_B19 & _LC1_B24
# !_LC1_B19 & _LC2_B24;
-- Node name is '|74138:76|:15' = '|74138:76|Y0N'
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = LCELL( _EQ029);
_EQ029 = _LC7_B14
# _LC8_B19
# _LC3_B14;
-- Node name is '|74138:76|:16' = '|74138:76|Y1N'
-- Equation name is '_LC5_B14', type is buried
_LC5_B14 = LCELL( _EQ030);
_EQ030 = _LC7_B14
# _LC8_B19
# !_LC3_B14;
-- Node name is '|74138:76|:17' = '|74138:76|Y2N'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ031);
_EQ031 = !_LC7_B14
# _LC8_B19
# _LC3_B14;
-- Node name is '|74138:76|:20' = '|74138:76|Y5N'
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = LCELL( _EQ032);
_EQ032 = _LC7_B14
# !_LC8_B19
# !_LC3_B14;
Project Information d:\luogical experiment\the 8st\pinlvji\xianshidianlu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:07
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,377K
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