📄 xianshidianlu.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
136 - - - 20 OUTPUT 0 1 0 0 A
42 - - - 19 OUTPUT 0 1 0 0 B
41 - - - 20 OUTPUT 0 1 0 0 C
135 - - - 19 OUTPUT 0 1 0 0 D
143 - - A -- OUTPUT 0 1 0 0 E
137 - - - 20 OUTPUT 0 1 0 0 F
29 - - E -- OUTPUT 0 1 0 0 G
78 - - F -- OUTPUT 0 0 0 0 H
95 - - B -- OUTPUT 0 1 0 0 Y1
10 - - B -- OUTPUT 0 1 0 0 Y2
99 - - B -- OUTPUT 0 1 0 0 Y3
9 - - B -- OUTPUT 0 1 0 0 Y4
122 - - - 13 OUTPUT 0 1 0 0 Y5
49 - - - 14 OUTPUT 0 1 0 0 Y6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\xianshidianlu.rpt
xianshidianlu
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - B 19 OR2 s ! 2 2 0 1 |4santai:98|~1~1~1~2
- 4 - B 19 OR2 s ! 2 2 0 1 |4santai:98|~1~1~1~3
- 2 - B 19 OR2 s ! 1 2 0 1 |4santai:98|~1~1~1~4
- 7 - B 20 OR2 1 3 0 7 |4santai:98|~1~1~1
- 6 - B 24 OR2 s 2 2 0 1 |4santai:98|~2~1~1~2
- 7 - B 24 OR2 s 1 2 0 1 |4santai:98|~2~1~1~3
- 8 - B 24 OR2 s 2 2 0 1 |4santai:98|~2~1~1~4
- 1 - B 24 OR2 ! 1 3 0 7 |4santai:98|~2~1~1
- 5 - B 19 OR2 s ! 2 2 0 1 |4santai:98|~3~1~1~2
- 6 - B 19 OR2 s ! 1 2 0 1 |4santai:98|~3~1~1~3
- 7 - B 19 OR2 s ! 2 2 0 1 |4santai:98|~3~1~1~4
- 1 - B 19 OR2 ! 1 3 0 7 |4santai:98|~3~1~1
- 3 - B 24 OR2 s ! 2 2 0 1 |4santai:98|~4~1~1~2
- 4 - B 24 OR2 s ! 1 2 0 1 |4santai:98|~4~1~1~3
- 5 - B 24 OR2 s ! 2 2 0 1 |4santai:98|~4~1~1~4
- 2 - B 24 OR2 ! 1 3 0 5 |4santai:98|~4~1~1
- 3 - B 14 DFFE + ! 0 2 0 7 |05jishuqi:46|Q1 (|05jishuqi:46|:1)
- 7 - B 14 DFFE + ! 0 2 0 7 |05jishuqi:46|Q2 (|05jishuqi:46|:2)
- 8 - B 19 DFFE + ! 0 2 0 8 |05jishuqi:46|Q3 (|05jishuqi:46|:3)
- 8 - B 14 OR2 ! 0 3 1 5 |05jishuqi:46|:15
- 4 - B 14 OR2 ! 0 3 1 5 |05jishuqi:46|:16
- 2 - B 20 OR2 0 4 1 0 |7449:18|OC (|7449:18|:31)
- 1 - B 20 OR2 0 3 1 0 |7449:18|OE (|7449:18|:32)
- 8 - B 20 OR2 0 4 1 0 |7449:18|OG (|7449:18|:33)
- 4 - B 20 OR2 0 4 1 0 |7449:18|OA (|7449:18|:34)
- 6 - B 20 OR2 0 4 1 0 |7449:18|OB (|7449:18|:35)
- 3 - B 20 OR2 0 3 1 0 |7449:18|OD (|7449:18|:36)
- 5 - B 20 OR2 0 4 1 0 |7449:18|OF (|7449:18|:37)
- 6 - B 14 OR2 0 3 1 4 |74138:76|Y0N (|74138:76|:15)
- 5 - B 14 OR2 0 3 1 4 |74138:76|Y1N (|74138:76|:16)
- 1 - B 14 OR2 0 3 1 4 |74138:76|Y2N (|74138:76|:17)
- 2 - B 14 OR2 0 3 1 4 |74138:76|Y5N (|74138:76|:20)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\xianshidianlu.rpt
xianshidianlu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 12/ 96( 12%) 0/ 48( 0%) 21/ 48( 43%) 3/16( 18%) 4/16( 25%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
15: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
16: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
20: 5/24( 20%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
21: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\xianshidianlu.rpt
xianshidianlu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 CLK
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\xianshidianlu.rpt
xianshidianlu
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 3 PR_L
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\xianshidianlu.rpt
xianshidianlu
** EQUATIONS **
CLK : INPUT;
N0 : INPUT;
N1 : INPUT;
N2 : INPUT;
N3 : INPUT;
N4 : INPUT;
N5 : INPUT;
N6 : INPUT;
N7 : INPUT;
N8 : INPUT;
N9 : INPUT;
N10 : INPUT;
N11 : INPUT;
N12 : INPUT;
N13 : INPUT;
N14 : INPUT;
N15 : INPUT;
N16 : INPUT;
N17 : INPUT;
N18 : INPUT;
N19 : INPUT;
N20 : INPUT;
N21 : INPUT;
N22 : INPUT;
N23 : INPUT;
PR_L : INPUT;
-- Node name is 'A'
-- Equation name is 'A', type is output
A = _LC4_B20;
-- Node name is 'B'
-- Equation name is 'B', type is output
B = _LC6_B20;
-- Node name is 'C'
-- Equation name is 'C', type is output
C = _LC2_B20;
-- Node name is 'D'
-- Equation name is 'D', type is output
D = _LC3_B20;
-- Node name is 'E'
-- Equation name is 'E', type is output
E = _LC1_B20;
-- Node name is 'F'
-- Equation name is 'F', type is output
F = _LC5_B20;
-- Node name is 'G'
-- Equation name is 'G', type is output
G = _LC8_B20;
-- Node name is 'H'
-- Equation name is 'H', type is output
H = GND;
-- Node name is 'Y1'
-- Equation name is 'Y1', type is output
Y1 = !_LC6_B14;
-- Node name is 'Y2'
-- Equation name is 'Y2', type is output
Y2 = !_LC5_B14;
-- Node name is 'Y3'
-- Equation name is 'Y3', type is output
Y3 = !_LC1_B14;
-- Node name is 'Y4'
-- Equation name is 'Y4', type is output
Y4 = _LC4_B14;
-- Node name is 'Y5'
-- Equation name is 'Y5', type is output
Y5 = _LC8_B14;
-- Node name is 'Y6'
-- Equation name is 'Y6', type is output
Y6 = !_LC2_B14;
-- Node name is '|4santai:98|~1~1~1~2'
-- Equation name is '_LC3_B19', type is buried
-- synthesized logic cell
!_LC3_B19 = _LC3_B19~NOT;
_LC3_B19~NOT = LCELL( _EQ001);
_EQ001 = N4 & N8
# _LC1_B14 & N4
# _LC5_B14 & N8
# _LC1_B14 & _LC5_B14;
-- Node name is '|4santai:98|~1~1~1~3'
-- Equation name is '_LC4_B19', type is buried
-- synthesized logic cell
!_LC4_B19 = _LC4_B19~NOT;
_LC4_B19~NOT = LCELL( _EQ002);
_EQ002 = N12 & N16
# !_LC8_B14 & N12
# !_LC4_B14 & N16
# !_LC4_B14 & !_LC8_B14;
-- Node name is '|4santai:98|~1~1~1~4'
-- Equation name is '_LC2_B19', type is buried
-- synthesized logic cell
!_LC2_B19 = _LC2_B19~NOT;
_LC2_B19~NOT = LCELL( _EQ003);
_EQ003 = !_LC4_B19 & N20
# _LC2_B14 & !_LC4_B19;
-- Node name is '|4santai:98|~1~1~1'
-- Equation name is '_LC7_B20', type is buried
_LC7_B20 = LCELL( _EQ004);
_EQ004 = !_LC2_B19 & !_LC3_B19 & N0
# !_LC2_B19 & !_LC3_B19 & _LC6_B14;
-- Node name is '|4santai:98|~2~1~1~2'
-- Equation name is '_LC6_B24', type is buried
-- synthesized logic cell
_LC6_B24 = LCELL( _EQ005);
_EQ005 = _LC8_B14 & !N17
# _LC4_B14 & !N13;
-- Node name is '|4santai:98|~2~1~1~3'
-- Equation name is '_LC7_B24', type is buried
-- synthesized logic cell
_LC7_B24 = LCELL( _EQ006);
_EQ006 = !_LC2_B14 & !N21
# _LC6_B24;
-- Node name is '|4santai:98|~2~1~1~4'
-- Equation name is '_LC8_B24', type is buried
-- synthesized logic cell
_LC8_B24 = LCELL( _EQ007);
_EQ007 = !_LC1_B14 & !N9
# !_LC5_B14 & !N5;
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