📄 jishuqi.rpt
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LC4 -> * * * * - - - - | * - | <-- Q16
LC5 -> * * * * - - - - | * - | <-- Q17
LC6 -> * - * * - - - - | * - | <-- Q18
LC8 -> * * * * * * * * | * - | <-- Q19
LC10 -> - - - - * * * * | * - | <-- Q20
LC11 -> - - - - * * * * | * - | <-- Q21
LC12 -> - - - - * - * * | * - | <-- Q22
LC13 -> - - - - * * * * | * - | <-- Q23
Pin
1 -> - - - - - - - - | - - | <-- CLR_L
LC17 -> * * * * - - - - | * * | <-- Q15
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\jishuqi.rpt
jishuqi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC27 Q0
| +----------------------------- LC31 Q1
| | +--------------------------- LC30 Q2
| | | +------------------------- LC29 Q3
| | | | +----------------------- LC24 Q4
| | | | | +--------------------- LC28 Q5
| | | | | | +------------------- LC32 Q6
| | | | | | | +----------------- LC26 Q7
| | | | | | | | +--------------- LC25 Q8
| | | | | | | | | +------------- LC18 Q9
| | | | | | | | | | +----------- LC19 Q10
| | | | | | | | | | | +--------- LC20 Q11
| | | | | | | | | | | | +------- LC21 Q12
| | | | | | | | | | | | | +----- LC22 Q13
| | | | | | | | | | | | | | +--- LC23 Q14
| | | | | | | | | | | | | | | +- LC17 Q15
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC27 -> * * * * - - - - - - - - - - - - | - * | <-- Q0
LC31 -> * * * * - - - - - - - - - - - - | - * | <-- Q1
LC30 -> * - * * - - - - - - - - - - - - | - * | <-- Q2
LC29 -> * * * * * * * * - - - - - - - - | - * | <-- Q3
LC24 -> - - - - * * * * - - - - - - - - | - * | <-- Q4
LC28 -> - - - - * * * * - - - - - - - - | - * | <-- Q5
LC32 -> - - - - * - * * - - - - - - - - | - * | <-- Q6
LC26 -> - - - - * * * * * * * * - - - - | - * | <-- Q7
LC25 -> - - - - - - - - * * * * - - - - | - * | <-- Q8
LC18 -> - - - - - - - - * * * * - - - - | - * | <-- Q9
LC19 -> - - - - - - - - * - * * - - - - | - * | <-- Q10
LC20 -> - - - - - - - - * * * * * * * * | - * | <-- Q11
LC21 -> - - - - - - - - - - - - * * * * | - * | <-- Q12
LC22 -> - - - - - - - - - - - - * * * * | - * | <-- Q13
LC23 -> - - - - - - - - - - - - * - * * | - * | <-- Q14
LC17 -> - - - - - - - - - - - - * * * * | * * | <-- Q15
Pin
1 -> - - - - - - - - - - - - - - - - | - - | <-- CLR_L
4 -> * * * * - - - - - - - - - - - - | - * | <-- CP
5 -> * * * * - - - - - - - - - - - - | - * | <-- EN
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:d:\luogical experiment\the 8st\pinlvji\jishuqi.rpt
jishuqi
** EQUATIONS **
CLR_L : INPUT;
CP : INPUT;
EN : INPUT;
-- Node name is 'Q0' = '|09jishuqi:4|Q0'
-- Equation name is 'Q0', type is output
Q0 = DFFE( _EQ001 $ GND, _EQ002, GLOBAL( CLR_L), VCC, VCC);
_EQ001 = !Q0 & !Q1 & !Q2
# !Q0 & !Q3;
_EQ002 = CP & EN;
-- Node name is 'Q1' = '|09jishuqi:4|Q1'
-- Equation name is 'Q1', type is output
Q1 = DFFE( _EQ003 $ GND, _EQ004, GLOBAL( CLR_L), VCC, VCC);
_EQ003 = Q0 & !Q1 & !Q3
# !Q0 & Q1 & !Q3;
_EQ004 = CP & EN;
-- Node name is 'Q2' = '|09jishuqi:4|Q2'
-- Equation name is 'Q2', type is output
Q2 = DFFE( _EQ005 $ GND, _EQ006, GLOBAL( CLR_L), VCC, VCC);
_EQ005 = Q0 & Q1 & !Q2 & !Q3
# !Q0 & Q2 & !Q3
# !Q1 & Q2 & !Q3;
_EQ006 = CP & EN;
-- Node name is 'Q3' = '|09jishuqi:4|Q3'
-- Equation name is 'Q3', type is output
Q3 = DFFE( _EQ007 $ GND, _EQ008, GLOBAL( CLR_L), VCC, VCC);
_EQ007 = Q0 & Q1 & Q2 & !Q3
# !Q0 & !Q1 & !Q2 & Q3;
_EQ008 = CP & EN;
-- Node name is 'Q4' = '|09jishuqi:6|Q0'
-- Equation name is 'Q4', type is output
Q4 = DFFE( _EQ009 $ GND, !Q3, GLOBAL( CLR_L), VCC, VCC);
_EQ009 = !Q4 & !Q5 & !Q6
# !Q4 & !Q7;
-- Node name is 'Q5' = '|09jishuqi:6|Q1'
-- Equation name is 'Q5', type is output
Q5 = DFFE( _EQ010 $ GND, !Q3, GLOBAL( CLR_L), VCC, VCC);
_EQ010 = Q4 & !Q5 & !Q7
# !Q4 & Q5 & !Q7;
-- Node name is 'Q6' = '|09jishuqi:6|Q2'
-- Equation name is 'Q6', type is output
Q6 = DFFE( _EQ011 $ GND, !Q3, GLOBAL( CLR_L), VCC, VCC);
_EQ011 = Q4 & Q5 & !Q6 & !Q7
# !Q4 & Q6 & !Q7
# !Q5 & Q6 & !Q7;
-- Node name is 'Q7' = '|09jishuqi:6|Q3'
-- Equation name is 'Q7', type is output
Q7 = DFFE( _EQ012 $ GND, !Q3, GLOBAL( CLR_L), VCC, VCC);
_EQ012 = Q4 & Q5 & Q6 & !Q7
# !Q4 & !Q5 & !Q6 & Q7;
-- Node name is 'Q8' = '|09jishuqi:5|Q0'
-- Equation name is 'Q8', type is output
Q8 = DFFE( _EQ013 $ GND, !Q7, GLOBAL( CLR_L), VCC, VCC);
_EQ013 = !Q8 & !Q9 & !Q10
# !Q8 & !Q11;
-- Node name is 'Q9' = '|09jishuqi:5|Q1'
-- Equation name is 'Q9', type is output
Q9 = DFFE( _EQ014 $ GND, !Q7, GLOBAL( CLR_L), VCC, VCC);
_EQ014 = Q8 & !Q9 & !Q11
# !Q8 & Q9 & !Q11;
-- Node name is 'Q10' = '|09jishuqi:5|Q2'
-- Equation name is 'Q10', type is output
Q10 = DFFE( _EQ015 $ GND, !Q7, GLOBAL( CLR_L), VCC, VCC);
_EQ015 = Q8 & Q9 & !Q10 & !Q11
# !Q8 & Q10 & !Q11
# !Q9 & Q10 & !Q11;
-- Node name is 'Q11' = '|09jishuqi:5|Q3'
-- Equation name is 'Q11', type is output
Q11 = DFFE( _EQ016 $ GND, !Q7, GLOBAL( CLR_L), VCC, VCC);
_EQ016 = Q8 & Q9 & Q10 & !Q11
# !Q8 & !Q9 & !Q10 & Q11;
-- Node name is 'Q12' = '|09jishuqi:9|Q0'
-- Equation name is 'Q12', type is output
Q12 = DFFE( _EQ017 $ GND, !Q11, GLOBAL( CLR_L), VCC, VCC);
_EQ017 = !Q12 & !Q13 & !Q14
# !Q12 & !Q15;
-- Node name is 'Q13' = '|09jishuqi:9|Q1'
-- Equation name is 'Q13', type is output
Q13 = DFFE( _EQ018 $ GND, !Q11, GLOBAL( CLR_L), VCC, VCC);
_EQ018 = Q12 & !Q13 & !Q15
# !Q12 & Q13 & !Q15;
-- Node name is 'Q14' = '|09jishuqi:9|Q2'
-- Equation name is 'Q14', type is output
Q14 = DFFE( _EQ019 $ GND, !Q11, GLOBAL( CLR_L), VCC, VCC);
_EQ019 = Q12 & Q13 & !Q14 & !Q15
# !Q12 & Q14 & !Q15
# !Q13 & Q14 & !Q15;
-- Node name is 'Q15' = '|09jishuqi:9|Q3'
-- Equation name is 'Q15', type is output
Q15 = DFFE( _EQ020 $ GND, !Q11, GLOBAL( CLR_L), VCC, VCC);
_EQ020 = Q12 & Q13 & Q14 & !Q15
# !Q12 & !Q13 & !Q14 & Q15;
-- Node name is 'Q16' = '|09jishuqi:7|Q0'
-- Equation name is 'Q16', type is output
Q16 = DFFE( _EQ021 $ GND, !Q15, GLOBAL( CLR_L), VCC, VCC);
_EQ021 = !Q16 & !Q17 & !Q18
# !Q16 & !Q19;
-- Node name is 'Q17' = '|09jishuqi:7|Q1'
-- Equation name is 'Q17', type is output
Q17 = DFFE( _EQ022 $ GND, !Q15, GLOBAL( CLR_L), VCC, VCC);
_EQ022 = Q16 & !Q17 & !Q19
# !Q16 & Q17 & !Q19;
-- Node name is 'Q18' = '|09jishuqi:7|Q2'
-- Equation name is 'Q18', type is output
Q18 = DFFE( _EQ023 $ GND, !Q15, GLOBAL( CLR_L), VCC, VCC);
_EQ023 = Q16 & Q17 & !Q18 & !Q19
# !Q16 & Q18 & !Q19
# !Q17 & Q18 & !Q19;
-- Node name is 'Q19' = '|09jishuqi:7|Q3'
-- Equation name is 'Q19', type is output
Q19 = DFFE( _EQ024 $ GND, !Q15, GLOBAL( CLR_L), VCC, VCC);
_EQ024 = Q16 & Q17 & Q18 & !Q19
# !Q16 & !Q17 & !Q18 & Q19;
-- Node name is 'Q20' = '|09jishuqi:8|Q0'
-- Equation name is 'Q20', type is output
Q20 = DFFE( _EQ025 $ GND, !Q19, GLOBAL( CLR_L), VCC, VCC);
_EQ025 = !Q20 & !Q21 & !Q22
# !Q20 & !Q23;
-- Node name is 'Q21' = '|09jishuqi:8|Q1'
-- Equation name is 'Q21', type is output
Q21 = DFFE( _EQ026 $ GND, !Q19, GLOBAL( CLR_L), VCC, VCC);
_EQ026 = Q20 & !Q21 & !Q23
# !Q20 & Q21 & !Q23;
-- Node name is 'Q22' = '|09jishuqi:8|Q2'
-- Equation name is 'Q22', type is output
Q22 = DFFE( _EQ027 $ GND, !Q19, GLOBAL( CLR_L), VCC, VCC);
_EQ027 = Q20 & Q21 & !Q22 & !Q23
# !Q20 & Q22 & !Q23
# !Q21 & Q22 & !Q23;
-- Node name is 'Q23' = '|09jishuqi:8|Q3'
-- Equation name is 'Q23', type is output
Q23 = DFFE( _EQ028 $ GND, !Q19, GLOBAL( CLR_L), VCC, VCC);
_EQ028 = Q20 & Q21 & Q22 & !Q23
# !Q20 & !Q21 & !Q22 & Q23;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\luogical experiment\the 8st\pinlvji\jishuqi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,171K
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