zonghe.rpt

在max_plus2和FPGA实验箱上实现频率计的功能

-- Node name is '|xianshi:28|7449:49|~35~1' = '|xianshi:28|7449:49|OB~1' 
-- Equation name is '_LC5_A16', type is buried 
-- synthesized logic cell 
_LC5_A16 = LCELL( _EQ023);
  _EQ023 = !_LC1_A16 & !_LC6_A18
         # !_LC1_A16 &  _LC4_A20
         # !_LC1_A16 & !_LC8_A20;

-- Node name is '|xianshi:28|7449:49|:31' = '|xianshi:28|7449:49|OC' 
-- Equation name is '_LC6_A16', type is buried 
_LC6_A16 = LCELL( _EQ024);
  _EQ024 = !_LC3_A18 &  _LC8_A20
         # !_LC5_A20 &  _LC8_A20
         # !_LC3_A18 &  _LC7_A18
         # !_LC5_A20 &  _LC7_A18;

-- Node name is '|xianshi:28|7449:49|:36' = '|xianshi:28|7449:49|OD' 
-- Equation name is '_LC1_A18', type is buried 
_LC1_A18 = LCELL( _EQ025);
  _EQ025 =  _LC4_A20 & !_LC8_A20
         #  _LC4_A18
         # !_LC2_A20 & !_LC8_A20
         # !_LC2_A20 &  _LC4_A20
         #  _LC2_A20 & !_LC4_A20 &  _LC8_A20;

-- Node name is '|xianshi:28|7449:49|:32' = '|xianshi:28|7449:49|OE' 
-- Equation name is '_LC2_A18', type is buried 
_LC2_A18 = LCELL( _EQ026);
  _EQ026 = !_LC2_A20 & !_LC3_A18
         # !_LC3_A18 &  _LC4_A18
         # !_LC2_A20 &  _LC4_A20
         #  _LC4_A18 &  _LC4_A20;

-- Node name is '|xianshi:28|7449:49|:37' = '|xianshi:28|7449:49|OF' 
-- Equation name is '_LC8_A18', type is buried 
_LC8_A18 = LCELL( _EQ027);
  _EQ027 =  _LC3_A16 & !_LC6_A18
         # !_LC6_A18 &  _LC8_A20
         #  _LC3_A16 & !_LC4_A20
         # !_LC4_A20 &  _LC8_A20;

-- Node name is '|xianshi:28|7449:49|~37~1' = '|xianshi:28|7449:49|OF~1' 
-- Equation name is '_LC3_A16', type is buried 
-- synthesized logic cell 
_LC3_A16 = LCELL( _EQ028);
  _EQ028 = !_LC4_A20 & !_LC6_A18
         # !_LC4_A20 &  _LC5_A20
         #  _LC4_A18 & !_LC6_A18
         #  _LC4_A18 &  _LC5_A20;

-- Node name is '|xianshi:28|7449:49|:33' = '|xianshi:28|7449:49|OG' 
-- Equation name is '_LC4_A16', type is buried 
_LC4_A16 = LCELL( _EQ029);
  _EQ029 = !_LC6_A18 & !_LC7_A16
         # !_LC4_A20 & !_LC7_A16
         # !_LC7_A16 & !_LC8_A20;

-- Node name is '|xianshi:28|7449:49|:1' 
-- Equation name is '_LC2_A16', type is buried 
!_LC2_A16 = _LC2_A16~NOT;
_LC2_A16~NOT = LCELL( _EQ030);
  _EQ030 = !_LC6_A18
         #  _LC5_A20
         #  _LC8_A20
         #  _LC4_A20;

-- Node name is '|xianshi:28|7449:49|:24' 
-- Equation name is '_LC1_A16', type is buried 
!_LC1_A16 = _LC1_A16~NOT;
_LC1_A16~NOT = LCELL( _EQ031);
  _EQ031 = !_LC4_A20
         #  _LC4_A18
         # !_LC5_A20;

-- Node name is '|xianshi:28|7449:49|:45' 
-- Equation name is '_LC7_A16', type is buried 
!_LC7_A16 = _LC7_A16~NOT;
_LC7_A16~NOT = LCELL( _EQ032);
  _EQ032 = !_LC4_A18 &  _LC4_A20
         # !_LC4_A18 &  _LC5_A20
         #  _LC3_A18;

-- Node name is '|xianshi:28|7449:49|~51~1' 
-- Equation name is '_LC7_A18', type is buried 
-- synthesized logic cell 
_LC7_A18 = LCELL( _EQ033);
  _EQ033 =  _LC2_A20
         # !_LC4_A20
         #  _LC4_A18;

-- Node name is '|xianshi:28|74138:29|:15' = '|xianshi:28|74138:29|Y0N' 
-- Equation name is '_LC5_A18', type is buried 
!_LC5_A18 = _LC5_A18~NOT;
_LC5_A18~NOT = LCELL( _EQ034);
  _EQ034 = !_LC5_A19 & !_LC7_A19 & !_LC8_A19;

-- Node name is '|xianshi:28|74138:29|:16' = '|xianshi:28|74138:29|Y1N' 
-- Equation name is '_LC1_A19', type is buried 
!_LC1_A19 = _LC1_A19~NOT;
_LC1_A19~NOT = LCELL( _EQ035);
  _EQ035 =  _LC5_A19 & !_LC7_A19 & !_LC8_A19;

-- Node name is '|xianshi:28|74138:29|:17' = '|xianshi:28|74138:29|Y2N' 
-- Equation name is '_LC2_A19', type is buried 
!_LC2_A19 = _LC2_A19~NOT;
_LC2_A19~NOT = LCELL( _EQ036);
  _EQ036 = !_LC5_A19 &  _LC7_A19 & !_LC8_A19;

-- Node name is '|xianshi:28|74138:29|:20' = '|xianshi:28|74138:29|Y5N' 
-- Equation name is '_LC3_A19', type is buried 
!_LC3_A19 = _LC3_A19~NOT;
_LC3_A19~NOT = LCELL( _EQ037);
  _EQ037 =  _LC5_A19 & !_LC7_A19 &  _LC8_A19;

-- Node name is '|xianshi:28|74153:38|:1' 
-- Equation name is '_LC6_A18', type is buried 
!_LC6_A18 = _LC6_A18~NOT;
_LC6_A18~NOT = LCELL( _EQ038);
  _EQ038 = !_LC2_A20
         #  _LC4_A18;

-- Node name is '|xianshi:28|74153:38|~5~1' 
-- Equation name is '_LC4_A18', type is buried 
-- synthesized logic cell 
_LC4_A18 = LCELL( _EQ039);
  _EQ039 = !_LC7_A19 &  _LC8_A19
         #  _LC7_A19 & !_LC8_A19;

-- Node name is '|xianshi:28|74153:40|:1' 
-- Equation name is '_LC3_A18', type is buried 
!_LC3_A18 = _LC3_A18~NOT;
_LC3_A18~NOT = LCELL( _EQ040);
  _EQ040 = !_LC8_A20
         #  _LC4_A18;

-- Node name is '|xianshi:28|74157:39|:22' = '|xianshi:28|74157:39|Y1' 
-- Equation name is '_LC2_A20', type is buried 
_LC2_A20 = LCELL( _EQ041);
  _EQ041 = !_LC1_A19 &  _LC6_A20
         #  _LC4_A21 & !_LC5_A18;

-- Node name is '|xianshi:28|74157:39|:23' = '|xianshi:28|74157:39|Y2' 
-- Equation name is '_LC4_A20', type is buried 
!_LC4_A20 = _LC4_A20~NOT;
_LC4_A20~NOT = LCELL( _EQ042);
  _EQ042 =  _LC1_A19 &  _LC5_A18
         # !_LC3_A20 &  _LC5_A18
         #  _LC1_A19 & !_LC1_A21
         # !_LC1_A21 & !_LC3_A20;

-- Node name is '|xianshi:28|74157:39|:24' = '|xianshi:28|74157:39|Y3' 
-- Equation name is '_LC8_A20', type is buried 
_LC8_A20 = LCELL( _EQ043);
  _EQ043 = !_LC1_A19 &  _LC7_A20
         #  _LC2_A21 & !_LC5_A18;

-- Node name is '|xianshi:28|74157:39|:25' = '|xianshi:28|74157:39|Y4' 
-- Equation name is '_LC5_A20', type is buried 
!_LC5_A20 = _LC5_A20~NOT;
_LC5_A20~NOT = LCELL( _EQ044);
  _EQ044 =  _LC1_A19 &  _LC5_A18
         # !_LC1_A20 &  _LC5_A18
         #  _LC1_A19 & !_LC3_A21
         # !_LC1_A20 & !_LC3_A21;



Project Information         e:\luogical  experiment\the 8st\pinlvji\zonghe.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,962K