📄 zonghe.rpt
字号:
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
RESERVED | 7 102 | RESERVED
RESERVED | 8 101 | Y1
RESERVED | 9 100 | Y2
RESERVED | 10 99 | Y3
RESERVED | 11 98 | Y4
RESERVED | 12 97 | Y5
RESERVED | 13 96 | Y6
RESERVED | 14 95 | RESERVED
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
RESERVED | 17 92 | RESERVED
RESERVED | 18 91 | RESERVED
RESERVED | 19 EPF10K20TI144-4 90 | RESERVED
RESERVED | 20 89 | RESERVED
RESERVED | 21 88 | RESERVED
RESERVED | 22 87 | RESERVED
RESERVED | 23 86 | RESERVED
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
RESERVED | 26 83 | RESERVED
RESERVED | 27 82 | RESERVED
RESERVED | 28 81 | RESERVED
RESERVED | 29 80 | RESERVED
RESERVED | 30 79 | RESERVED
RESERVED | 31 78 | RESERVED
RESERVED | 32 77 | ^MSEL0
RESERVED | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G R H G F V E D C B G A V V G G G G G R R V R R R R G R R R R V R
E E E N E C N C C N N N N N E E C E E E E N E E E E C E
S S S D S C D C C D D D D D S S C S S S S D S S S S C S
E E E I E I I I I I I I I I E E I E E E E I E E E E I E
R R R O R O O N N N N N N N R R O R R R R O R R R R O R
V V V V T T T T T T T V V V V V V V V V V V
E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:e:\luogical experiment\the 8st\pinlvji\zonghe.rpt
zonghe
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 4/22( 18%)
A14 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 2/22( 9%)
A16 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 8/22( 36%)
A18 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 0/2 0/2 7/22( 31%)
A19 8/ 8(100%) 5/ 8( 62%) 4/ 8( 50%) 1/2 0/2 1/22( 4%)
A20 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
A21 4/ 8( 50%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 1/6 ( 16%)
Total I/O pins used: 16/96 ( 16%)
Total logic cells used: 44/1152 ( 3%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.47/4 ( 86%)
Total fan-in: 153/4608 ( 3%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 14
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 44
Total flipflops required: 15
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 4/1152 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 7 0 8 0 8 8 8 4 0 0 0 44/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 7 0 8 0 8 8 8 4 0 0 0 44/0
Device-Specific Information:e:\luogical experiment\the 8st\pinlvji\zonghe.rpt
zonghe
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
128 - - - 13 INPUT 0 0 0 3 CK
125 - - - -- INPUT 0 0 0 1 CP
122 - - - 13 INPUT 0 0 0 4 KCP
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\luogical experiment\the 8st\pinlvji\zonghe.rpt
zonghe
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
51 - - - 14 OUTPUT 0 0 0 0 A
49 - - - 14 OUTPUT 0 1 0 0 B
48 - - - 15 OUTPUT 0 1 0 0 C
47 - - - 16 OUTPUT 0 1 0 0 D
46 - - - 17 OUTPUT 0 1 0 0 E
44 - - - 18 OUTPUT 0 1 0 0 F
43 - - - 18 OUTPUT 0 1 0 0 G
42 - - - 19 OUTPUT 0 1 0 0 H
101 - - A -- OUTPUT 0 1 0 0 Y1
100 - - A -- OUTPUT 0 1 0 0 Y2
99 - - B -- OUTPUT 0 1 0 0 Y3
98 - - B -- OUTPUT 0 1 0 0 Y4
97 - - B -- OUTPUT 0 1 0 0 Y5
96 - - B -- OUTPUT 0 1 0 0 Y6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\luogical experiment\the 8st\pinlvji\zonghe.rpt
zonghe
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 21 DFFE 0 5 0 8 |jishuqi:1|09jishuqi:4|Q3 (|jishuqi:1|09jishuqi:4|:12)
- 2 - A 21 DFFE 0 5 0 3 |jishuqi:1|09jishuqi:4|Q2 (|jishuqi:1|09jishuqi:4|:13)
- 1 - A 21 DFFE 0 4 0 4 |jishuqi:1|09jishuqi:4|Q1 (|jishuqi:1|09jishuqi:4|:14)
- 4 - A 21 DFFE 0 5 0 4 |jishuqi:1|09jishuqi:4|Q0 (|jishuqi:1|09jishuqi:4|:15)
- 1 - A 20 DFFE 0 5 0 4 |jishuqi:1|09jishuqi:6|Q3 (|jishuqi:1|09jishuqi:6|:12)
- 7 - A 20 DFFE 0 5 0 3 |jishuqi:1|09jishuqi:6|Q2 (|jishuqi:1|09jishuqi:6|:13)
- 3 - A 20 DFFE 0 4 0 4 |jishuqi:1|09jishuqi:6|Q1 (|jishuqi:1|09jishuqi:6|:14)
- 6 - A 20 DFFE 0 5 0 4 |jishuqi:1|09jishuqi:6|Q0 (|jishuqi:1|09jishuqi:6|:15)
- 4 - A 14 AND2 1 2 0 4 |jishuqi:1|7408:14|1 (|jishuqi:1|7408:14|:4)
- 1 - A 14 OR2 ! 0 4 0 8 |kongzhidianlu:3|ENCLR (|kongzhidianlu:3|:6)
- 5 - A 14 DFFE 1 3 0 5 |kongzhidianlu:3|08jishuqi:1|Q3 (|kongzhidianlu:3|08jishuqi:1|:12)
- 6 - A 14 DFFE 1 3 0 3 |kongzhidianlu:3|08jishuqi:1|Q2 (|kongzhidianlu:3|08jishuqi:1|:13)
- 3 - A 14 DFFE 1 2 0 4 |kongzhidianlu:3|08jishuqi:1|Q1 (|kongzhidianlu:3|08jishuqi:1|:14)
- 2 - A 14 DFFE 1 1 0 5 |kongzhidianlu:3|08jishuqi:1|Q0 (|kongzhidianlu:3|08jishuqi:1|:15)
- 7 - A 14 OR2 0 3 0 1 |kongzhidianlu:3|08jishuqi:1|7408:22|1 (|kongzhidianlu:3|08jishuqi:1|7408:22|:4)
- 5 - A 19 DFFE 1 2 0 8 |xianshi:28|05jishuqi:2|Q1 (|xianshi:28|05jishuqi:2|:1)
- 7 - A 19 DFFE 1 2 0 9 |xianshi:28|05jishuqi:2|Q2 (|xianshi:28|05jishuqi:2|:2)
- 8 - A 19 DFFE 1 3 0 9 |xianshi:28|05jishuqi:2|Q3 (|xianshi:28|05jishuqi:2|:3)
- 6 - A 19 AND2 0 3 1 0 |xianshi:28|05jishuqi:2|:15
- 4 - A 19 AND2 0 3 1 1 |xianshi:28|05jishuqi:2|:16
- 2 - A 16 OR2 ! 0 4 0 1 |xianshi:28|7449:49|:1
- 1 - A 16 OR2 ! 0 3 0 2 |xianshi:28|7449:49|:24
- 6 - A 16 OR2 0 4 1 0 |xianshi:28|7449:49|OC (|xianshi:28|7449:49|:31)
- 2 - A 18 OR2 0 4 1 0 |xianshi:28|7449:49|OE (|xianshi:28|7449:49|:32)
- 4 - A 16 OR2 0 4 1 0 |xianshi:28|7449:49|OG (|xianshi:28|7449:49|:33)
- 2 - A 13 OR2 0 4 1 0 |xianshi:28|7449:49|OA (|xianshi:28|7449:49|:34)
- 5 - A 16 OR2 s 0 4 0 1 |xianshi:28|7449:49|OB~1 (|xianshi:28|7449:49|~35~1)
- 8 - A 16 OR2 0 4 1 0 |xianshi:28|7449:49|OB (|xianshi:28|7449:49|:35)
- 1 - A 18 OR2 0 4 1 0 |xianshi:28|7449:49|OD (|xianshi:28|7449:49|:36)
- 3 - A 16 OR2 s 0 4 0 1 |xianshi:28|7449:49|OF~1 (|xianshi:28|7449:49|~37~1)
- 8 - A 18 OR2 0 4 1 0 |xianshi:28|7449:49|OF (|xianshi:28|7449:49|:37)
- 7 - A 16 OR2 ! 0 4 0 1 |xianshi:28|7449:49|:45
- 7 - A 18 OR2 s 0 3 0 1 |xianshi:28|7449:49|~51~1
- 5 - A 18 AND2 ! 0 3 1 4 |xianshi:28|74138:29|Y0N (|xianshi:28|74138:29|:15)
- 1 - A 19 AND2 ! 0 3 1 4 |xianshi:28|74138:29|Y1N (|xianshi:28|74138:29|:16)
- 2 - A 19 AND2 ! 0 3 1 0 |xianshi:28|74138:29|Y2N (|xianshi:28|74138:29|:17)
- 3 - A 19 AND2 ! 0 3 1 0 |xianshi:28|74138:29|Y5N (|xianshi:28|74138:29|:20)
- 6 - A 18 OR2 ! 0 2 0 5 |xianshi:28|74153:38|:1
- 4 - A 18 OR2 s 0 2 0 8 |xianshi:28|74153:38|~5~1
- 3 - A 18 OR2 ! 0 2 0 5 |xianshi:28|74153:40|:1
- 2 - A 20 OR2 0 4 0 6 |xianshi:28|74157:39|Y1 (|xianshi:28|74157:39|:22)
- 4 - A 20 OR2 ! 0 4 0 11 |xianshi:28|74157:39|Y2 (|xianshi:28|74157:39|:23)
- 8 - A 20 OR2 0 4 0 7 |xianshi:28|74157:39|Y3 (|xianshi:28|74157:39|:24)
- 5 - A 20 OR2 ! 0 4 0 5 |xianshi:28|74157:39|Y4 (|xianshi:28|74157:39|:25)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\luogical experiment\the 8st\pinlvji\zonghe.rpt
zonghe
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
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