📄 xianshi.rpt
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_EQ007 = !_LC6_C22 & _LC8_C22 & set
# _LC3_C22 & !set;
-- Node name is '|jishu10:k1|:8' = '|jishu10:k1|count3'
-- Equation name is '_LC7_C22', type is buried
_LC7_C22 = DFFE( _EQ008, clk9, !clear, VCC, VCC);
_EQ008 = !_LC5_C22 & !_LC6_C22 & _LC7_C22
# _LC5_C22 & !_LC6_C22 & !_LC7_C22 & set
# _LC7_C22 & !set;
-- Node name is '|jishu10:k1|LPM_ADD_SUB:88|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = LCELL( _EQ009);
_EQ009 = _LC2_C22 & _LC3_C22 & _LC4_C22;
-- Node name is '|jishu10:k1|LPM_ADD_SUB:88|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_C22', type is buried
_LC8_C22 = LCELL( _EQ010);
_EQ010 = _LC3_C22 & !_LC4_C22
# !_LC2_C22 & _LC3_C22
# _LC2_C22 & !_LC3_C22 & _LC4_C22;
-- Node name is '|jishu10:k1|:63'
-- Equation name is '_LC6_C22', type is buried
!_LC6_C22 = _LC6_C22~NOT;
_LC6_C22~NOT = LCELL( _EQ011);
_EQ011 = _LC3_C22
# _LC4_C22
# !_LC7_C22
# !_LC2_C22;
-- Node name is '|jishu10:k2|:11' = '|jishu10:k2|count0'
-- Equation name is '_LC1_C15', type is buried
_LC1_C15 = DFFE( _EQ012, GLOBAL( clk10), !clear, VCC, VCC);
_EQ012 = _LC1_C15 & !set
# !_LC1_C15 & set;
-- Node name is '|jishu10:k2|:10' = '|jishu10:k2|count1'
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = DFFE( _EQ013, GLOBAL( clk10), !clear, VCC, VCC);
_EQ013 = !_LC1_C15 & _LC2_C15 & !_LC6_C15
# _LC1_C15 & !_LC2_C15 & !_LC6_C15 & set
# _LC2_C15 & !set;
-- Node name is '|jishu10:k2|:9' = '|jishu10:k2|count2'
-- Equation name is '_LC8_C15', type is buried
_LC8_C15 = DFFE( _EQ014, GLOBAL( clk10), !clear, VCC, VCC);
_EQ014 = !_LC6_C15 & _LC7_C15 & set
# _LC8_C15 & !set;
-- Node name is '|jishu10:k2|:8' = '|jishu10:k2|count3'
-- Equation name is '_LC3_C15', type is buried
_LC3_C15 = DFFE( _EQ015, GLOBAL( clk10), !clear, VCC, VCC);
_EQ015 = _LC3_C15 & !_LC5_C15 & !_LC6_C15
# !_LC3_C15 & _LC5_C15 & !_LC6_C15 & set
# _LC3_C15 & !set;
-- Node name is '|jishu10:k2|LPM_ADD_SUB:88|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C15', type is buried
_LC5_C15 = LCELL( _EQ016);
_EQ016 = _LC1_C15 & _LC2_C15 & _LC8_C15;
-- Node name is '|jishu10:k2|LPM_ADD_SUB:88|addcore:adder|:68' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC7_C15', type is buried
_LC7_C15 = LCELL( _EQ017);
_EQ017 = !_LC2_C15 & _LC8_C15
# !_LC1_C15 & _LC8_C15
# _LC1_C15 & _LC2_C15 & !_LC8_C15;
-- Node name is '|jishu10:k2|:63'
-- Equation name is '_LC6_C15', type is buried
!_LC6_C15 = _LC6_C15~NOT;
_LC6_C15~NOT = LCELL( _EQ018);
_EQ018 = _LC8_C15
# _LC2_C15
# !_LC3_C15
# !_LC1_C15;
-- Node name is '|qiduanyima:g1|:324'
-- Equation name is '_LC7_C13', type is buried
!_LC7_C13 = _LC7_C13~NOT;
_LC7_C13~NOT = LCELL( _EQ019);
_EQ019 = _LC1_C22
# _LC3_C13
# _LC2_C13
# !_LC4_C15;
-- Node name is '|qiduanyima:g1|:348'
-- Equation name is '_LC7_C16', type is buried
!_LC7_C16 = _LC7_C16~NOT;
_LC7_C16~NOT = LCELL( _EQ020);
_EQ020 = _LC1_C22
# _LC3_C13
# !_LC2_C13
# _LC4_C15;
-- Node name is '|qiduanyima:g1|:360'
-- Equation name is '_LC3_C18', type is buried
!_LC3_C18 = _LC3_C18~NOT;
_LC3_C18~NOT = LCELL( _EQ021);
_EQ021 = _LC1_C22
# !_LC3_C13
# _LC2_C13
# _LC4_C15;
-- Node name is '|qiduanyima:g1|:372'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = LCELL( _EQ022);
_EQ022 = !_LC1_C22 & !_LC2_C13 & !_LC3_C13 & !_LC4_C15;
-- Node name is '|qiduanyima:g1|:377'
-- Equation name is '_LC8_C18', type is buried
_LC8_C18 = LCELL( _EQ023);
_EQ023 = _LC2_C13 & !_LC4_C15
# !_LC2_C13 & _LC4_C15
# _LC1_C22
# _LC2_C13 & !_LC3_C13
# !_LC3_C13 & _LC4_C15;
-- Node name is '|qiduanyima:g1|:408'
-- Equation name is '_LC1_C18', type is buried
_LC1_C18 = LCELL( _EQ024);
_EQ024 = _LC4_C18
# _LC1_C13;
-- Node name is '|qiduanyima:g1|:410'
-- Equation name is '_LC4_C18', type is buried
!_LC4_C18 = _LC4_C18~NOT;
_LC4_C18~NOT = LCELL( _EQ025);
_EQ025 = !_LC1_C22 & _LC2_C13 & !_LC4_C15
# !_LC1_C22 & _LC3_C13 & !_LC4_C15;
-- Node name is '|qiduanyima:g1|~441~1'
-- Equation name is '_LC5_C18', type is buried
-- synthesized logic cell
_LC5_C18 = LCELL( _EQ026);
_EQ026 = _LC1_C22 & _LC2_C13
# _LC1_C22 & _LC4_C15
# _LC2_C13 & !_LC3_C13
# !_LC3_C13 & !_LC4_C15
# _LC1_C22 & !_LC3_C13
# !_LC1_C22 & !_LC2_C13 & !_LC4_C15;
-- Node name is '|qiduanyima:g1|:441'
-- Equation name is '_LC6_C18', type is buried
_LC6_C18 = LCELL( _EQ027);
_EQ027 = !_LC3_C18 & _LC5_C18
# _LC1_C13;
-- Node name is '|qiduanyima:g1|:474'
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = LCELL( _EQ028);
_EQ028 = _LC1_C22
# _LC2_C13 & !_LC3_C13
# !_LC3_C13 & !_LC4_C15
# _LC2_C13 & !_LC4_C15
# !_LC2_C13 & _LC3_C13 & _LC4_C15;
-- Node name is '|qiduanyima:g1|:530'
-- Equation name is '_LC2_C18', type is buried
_LC2_C18 = LCELL( _EQ029);
_EQ029 = _LC1_C22
# !_LC4_C15
# !_LC2_C13 & !_LC3_C13
# _LC2_C13 & _LC3_C13;
-- Node name is '|qiduanyima:g1|:540'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = LCELL( _EQ030);
_EQ030 = !_LC4_C18
# _LC2_C18
# _LC7_C13
# _LC1_C13;
-- Node name is '|qiduanyima:g1|:573'
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = LCELL( _EQ031);
_EQ031 = _LC1_C13
# !_LC3_C18 & !_LC7_C13;
Project Information e:\bahe1\yima\xianshi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,493K
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