📄 xianshi.rpt
字号:
122 - - - 13 INPUT 0 0 0 4 clk9
55 - - - -- INPUT G 0 0 0 0 clk10
95 - - B -- INPUT 0 0 0 8 set
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\bahe1\yima\xianshi.rpt
xianshi
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
112 - - - 02 OUTPUT 0 0 0 0 jiedi
96 - - B -- OUTPUT 0 1 0 0 q0
8 - - A -- OUTPUT 0 1 0 0 q1
51 - - - 14 OUTPUT 0 1 0 0 y0
49 - - - 14 OUTPUT 0 1 0 0 y1
48 - - - 15 OUTPUT 0 1 0 0 y2
47 - - - 16 OUTPUT 0 1 0 0 y3
46 - - - 17 OUTPUT 0 1 0 0 y4
44 - - - 18 OUTPUT 0 1 0 0 y5
43 - - - 18 OUTPUT 0 1 0 0 y6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\bahe1\yima\xianshi.rpt
xianshi
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 22 OR2 0 3 0 9 |duolufuyong:w1|:328
- 4 - C 15 OR2 0 3 0 9 |duolufuyong:w1|:337
- 2 - C 13 OR2 0 3 0 9 |duolufuyong:w1|:346
- 3 - C 13 OR2 0 3 0 9 |duolufuyong:w1|:355
- 6 - C 13 DFFE +s 1 0 1 0 |jishu2:d1|count~1 (|jishu2:d1|~4~1)
- 8 - C 13 DFFE + 1 0 1 4 |jishu2:d1|count (|jishu2:d1|:4)
- 5 - C 22 AND2 0 3 0 1 |jishu10:k1|LPM_ADD_SUB:88|addcore:adder|:59
- 8 - C 22 OR2 0 3 0 1 |jishu10:k1|LPM_ADD_SUB:88|addcore:adder|:68
- 7 - C 22 DFFE 3 2 0 2 |jishu10:k1|count3 (|jishu10:k1|:8)
- 3 - C 22 DFFE 3 2 0 4 |jishu10:k1|count2 (|jishu10:k1|:9)
- 4 - C 22 DFFE 3 2 0 4 |jishu10:k1|count1 (|jishu10:k1|:10)
- 2 - C 22 DFFE 3 0 0 5 |jishu10:k1|count0 (|jishu10:k1|:11)
- 6 - C 22 OR2 ! 0 4 0 3 |jishu10:k1|:63
- 5 - C 15 AND2 0 3 0 1 |jishu10:k2|LPM_ADD_SUB:88|addcore:adder|:59
- 7 - C 15 OR2 0 3 0 1 |jishu10:k2|LPM_ADD_SUB:88|addcore:adder|:68
- 3 - C 15 DFFE + 2 2 0 2 |jishu10:k2|count3 (|jishu10:k2|:8)
- 8 - C 15 DFFE + 2 2 0 4 |jishu10:k2|count2 (|jishu10:k2|:9)
- 2 - C 15 DFFE + 2 2 0 4 |jishu10:k2|count1 (|jishu10:k2|:10)
- 1 - C 15 DFFE + 2 0 0 5 |jishu10:k2|count0 (|jishu10:k2|:11)
- 6 - C 15 OR2 ! 0 4 0 3 |jishu10:k2|:63
- 7 - C 13 OR2 ! 0 4 0 2 |qiduanyima:g1|:324
- 7 - C 16 OR2 ! 0 4 1 0 |qiduanyima:g1|:348
- 3 - C 18 OR2 ! 0 4 0 2 |qiduanyima:g1|:360
- 1 - C 13 AND2 0 4 0 4 |qiduanyima:g1|:372
- 8 - C 18 OR2 0 4 1 0 |qiduanyima:g1|:377
- 1 - C 18 OR2 0 2 1 0 |qiduanyima:g1|:408
- 4 - C 18 OR2 ! 0 4 0 2 |qiduanyima:g1|:410
- 5 - C 18 OR2 s 0 4 0 1 |qiduanyima:g1|~441~1
- 6 - C 18 OR2 0 3 1 0 |qiduanyima:g1|:441
- 1 - C 16 OR2 0 4 1 0 |qiduanyima:g1|:474
- 2 - C 18 OR2 0 4 0 1 |qiduanyima:g1|:530
- 4 - C 13 OR2 0 4 1 0 |qiduanyima:g1|:540
- 5 - C 13 OR2 0 3 1 0 |qiduanyima:g1|:573
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\bahe1\yima\xianshi.rpt
xianshi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
C: 2/ 96( 2%) 0/ 48( 0%) 17/ 48( 35%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 1/16( 6%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\bahe1\yima\xianshi.rpt
xianshi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk9
INPUT 4 clk10
INPUT 2 clk1
Device-Specific Information: e:\bahe1\yima\xianshi.rpt
xianshi
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 clear
INPUT 2 cle
Device-Specific Information: e:\bahe1\yima\xianshi.rpt
xianshi
** EQUATIONS **
cle : INPUT;
clear : INPUT;
clk1 : INPUT;
clk9 : INPUT;
clk10 : INPUT;
set : INPUT;
-- Node name is 'jiedi'
-- Equation name is 'jiedi', type is output
jiedi = GND;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = !_LC6_C13;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _LC8_C13;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC5_C13;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC4_C13;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = !_LC7_C16;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = _LC1_C16;
-- Node name is 'y4'
-- Equation name is 'y4', type is output
y4 = _LC6_C18;
-- Node name is 'y5'
-- Equation name is 'y5', type is output
y5 = _LC1_C18;
-- Node name is 'y6'
-- Equation name is 'y6', type is output
y6 = _LC8_C18;
-- Node name is '|duolufuyong:w1|:328'
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = LCELL( _EQ001);
_EQ001 = _LC7_C22 & !_LC8_C13
# _LC3_C15 & _LC8_C13;
-- Node name is '|duolufuyong:w1|:337'
-- Equation name is '_LC4_C15', type is buried
_LC4_C15 = LCELL( _EQ002);
_EQ002 = _LC3_C22 & !_LC8_C13
# _LC8_C13 & _LC8_C15;
-- Node name is '|duolufuyong:w1|:346'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = LCELL( _EQ003);
_EQ003 = _LC4_C22 & !_LC8_C13
# _LC2_C15 & _LC8_C13;
-- Node name is '|duolufuyong:w1|:355'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = LCELL( _EQ004);
_EQ004 = _LC2_C22 & !_LC8_C13
# _LC1_C15 & _LC8_C13;
-- Node name is '|jishu2:d1|:4' = '|jishu2:d1|count'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = DFFE(!_LC8_C13, GLOBAL( clk1), !cle, VCC, VCC);
-- Node name is '|jishu2:d1|~4~1' = '|jishu2:d1|count~1'
-- Equation name is '_LC6_C13', type is buried
-- synthesized logic cell
_LC6_C13 = DFFE(!_LC6_C13, GLOBAL( clk1), !cle, VCC, VCC);
-- Node name is '|jishu10:k1|:11' = '|jishu10:k1|count0'
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = DFFE( _EQ005, clk9, !clear, VCC, VCC);
_EQ005 = _LC2_C22 & !set
# !_LC2_C22 & set;
-- Node name is '|jishu10:k1|:10' = '|jishu10:k1|count1'
-- Equation name is '_LC4_C22', type is buried
_LC4_C22 = DFFE( _EQ006, clk9, !clear, VCC, VCC);
_EQ006 = !_LC2_C22 & _LC4_C22 & !_LC6_C22
# _LC2_C22 & !_LC4_C22 & !_LC6_C22 & set
# _LC4_C22 & !set;
-- Node name is '|jishu10:k1|:9' = '|jishu10:k1|count2'
-- Equation name is '_LC3_C22', type is buried
_LC3_C22 = DFFE( _EQ007, clk9, !clear, VCC, VCC);
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