yima2.vhd

使用max_plus2在FPGA下实现拔河游戏机的功能

library ieee;
use ieee.std_logic_1164.all;

entity yima2 is
port(m:in std_logic;
     q0,q1:out std_logic);
end yima2;

architecture one of yima2 is
 begin
  q0<=not m;
  q1<=m;
end one;