jishu2.vhd

来自「使用max_plus2在FPGA下实现拔河游戏机的功能」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jishu2 is
port(clk,clr:in std_logic;
               q:out std_logic);
end jishu2;

architecture rtl of jishu2 is
signal count:std_logic;
begin
  q<=count;
 process(clk,clr)
   begin
    if(clr='1')then
      count<='0';
    elsif(clk'event and clk='1')then
        if(count='1')then
           count<='0';
        else count<='1';
        end if;
    end if;
 end process;
end rtl;