baheyouxi.rpt
来自「使用max_plus2在FPGA下实现拔河游戏机的功能」· RPT 代码 · 共 1,017 行 · 第 1/4 页
RPT
1,017 行
# !_LC027 & !_LC033 & !_LC039;
_EQ032 = _LC040 & _LC043;
-- Node name is '|HEXIN:26|zonghejishu:u1|jkslect:u1|:5' = '|HEXIN:26|zonghejishu:u1|jkslect:u1|jout'
-- Equation name is '_LC039', type is buried
_LC039 = TFFE( _EQ033, GLOBAL( cp), VCC, VCC, VCC);
_EQ033 = bego & !_LC018 & _LC038 & _LC039 & !_LC048 & _X003
# bego & !_LC018 & !_LC038 & !_LC039 & _LC048 & _X003;
_X003 = EXP(!_LC034 & !_LC035 & _LC036);
-- Node name is '|HEXIN:26|zonghejishu:u1|~60~1'
-- Equation name is '_LC040', type is buried
-- synthesized logic cell
_LC040 = LCELL( _EQ034 $ GND);
_EQ034 = bego & !_LC018 & !_LC038 & _LC048 & _X003
# bego & !_LC018 & _LC038 & !_LC048 & _X003;
_X003 = EXP(!_LC034 & !_LC035 & _LC036);
-- Node name is '|JICUNQI:27|dchufa:u1|:3'
-- Equation name is '_LC026', type is buried
_LC026 = DFFE( left $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:27|dchufa:u2|:3'
-- Equation name is '_LC009', type is buried
_LC009 = DFFE( _LC026 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:27|dchufa:u3|:3'
-- Equation name is '_LC041', type is buried
_LC041 = DFFE( _LC009 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:27|dchufa:u4|:3'
-- Equation name is '_LC044', type is buried
_LC044 = DFFE( _LC041 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:27|~112~1'
-- Equation name is '_LC048', type is buried
-- synthesized logic cell
_LC048 = LCELL( _EQ035 $ GND);
_EQ035 = bego & _LC009 & _LC026 & _LC041 & _LC044
# bego & _LC009 & _LC048
# bego & _LC041 & _LC048
# bego & _LC044 & _LC048
# bego & _LC026 & _LC048;
-- Node name is '|JICUNQI:28|dchufa:u1|:3'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE( right $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:28|dchufa:u2|:3'
-- Equation name is '_LC046', type is buried
_LC046 = DFFE( _LC029 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:28|dchufa:u3|:3'
-- Equation name is '_LC045', type is buried
_LC045 = DFFE( _LC046 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:28|dchufa:u4|:3'
-- Equation name is '_LC042', type is buried
_LC042 = DFFE( _LC045 $ GND, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|JICUNQI:28|~112~1'
-- Equation name is '_LC038', type is buried
-- synthesized logic cell
_LC038 = LCELL( _EQ036 $ GND);
_EQ036 = bego & _LC029 & _LC042 & _LC045 & _LC046
# bego & _LC038 & _LC046
# bego & _LC038 & _LC045
# bego & _LC038 & _LC042
# bego & _LC029 & _LC038;
-- Node name is '|XIANSHI:20|duolufuyong:w1|~328~1'
-- Equation name is '_LC055', type is buried
-- synthesized logic cell
_LC055 = LCELL( _EQ037 $ GND);
_EQ037 = _LC031 & you
# _LC061 & !you;
-- Node name is '|XIANSHI:20|duolufuyong:w1|~337~1'
-- Equation name is '_LC050', type is buried
-- synthesized logic cell
_LC050 = LCELL( _EQ038 $ GND);
_EQ038 = _LC028 & you
# _LC054 & !you;
-- Node name is '|XIANSHI:20|duolufuyong:w1|~346~1'
-- Equation name is '_LC058', type is buried
-- synthesized logic cell
_LC058 = LCELL( _EQ039 $ GND);
_EQ039 = _LC023 & you
# _LC063 & !you;
-- Node name is '|XIANSHI:20|duolufuyong:w1|~355~1'
-- Equation name is '_LC060', type is buried
-- synthesized logic cell
_LC060 = LCELL( _EQ040 $ GND);
_EQ040 = _LC022 & you
# _LC047 & !you;
-- Node name is '|XIANSHI:20|jishu10:k1|:11' = '|XIANSHI:20|jishu10:k1|count0'
-- Equation name is '_LC047', type is buried
_LC047 = TFFE( bego, _LC018, !clearxianshi, VCC, VCC);
-- Node name is '|XIANSHI:20|jishu10:k1|:10' = '|XIANSHI:20|jishu10:k1|count1'
-- Equation name is '_LC063', type is buried
_LC063 = TFFE( _EQ041, _LC018, !clearxianshi, VCC, VCC);
_EQ041 = bego & _LC047 & _LC054 & !_LC063
# bego & _LC047 & !_LC061 & !_LC063
# bego & _LC047 & _LC063;
-- Node name is '|XIANSHI:20|jishu10:k1|:9' = '|XIANSHI:20|jishu10:k1|count2'
-- Equation name is '_LC054', type is buried
_LC054 = TFFE( _EQ042, _LC018, !clearxianshi, VCC, VCC);
_EQ042 = bego & _LC047 & _LC063;
-- Node name is '|XIANSHI:20|jishu10:k1|:8' = '|XIANSHI:20|jishu10:k1|count3'
-- Equation name is '_LC061', type is buried
_LC061 = TFFE( _EQ043, _LC018, !clearxianshi, VCC, VCC);
_EQ043 = bego & _LC047 & !_LC054 & _LC061 & !_LC063
# bego & _LC047 & _LC054 & _LC063;
-- Node name is '|XIANSHI:20|jishu10:k2|:11' = '|XIANSHI:20|jishu10:k2|count0'
-- Equation name is '_LC022', type is buried
_LC022 = TFFE( bego, _EQ044, !clearxianshi, VCC, VCC);
_EQ044 = !_LC034 & !_LC035 & _LC036;
-- Node name is '|XIANSHI:20|jishu10:k2|:10' = '|XIANSHI:20|jishu10:k2|count1'
-- Equation name is '_LC023', type is buried
_LC023 = TFFE( _EQ045, _EQ046, !clearxianshi, VCC, VCC);
_EQ045 = bego & _LC022 & !_LC023 & _LC028
# bego & _LC022 & !_LC023 & !_LC031
# bego & _LC022 & _LC023;
_EQ046 = !_LC034 & !_LC035 & _LC036;
-- Node name is '|XIANSHI:20|jishu10:k2|:9' = '|XIANSHI:20|jishu10:k2|count2'
-- Equation name is '_LC028', type is buried
_LC028 = TFFE( _EQ047, _EQ048, !clearxianshi, VCC, VCC);
_EQ047 = bego & _LC022 & _LC023;
_EQ048 = !_LC034 & !_LC035 & _LC036;
-- Node name is '|XIANSHI:20|jishu10:k2|:8' = '|XIANSHI:20|jishu10:k2|count3'
-- Equation name is '_LC031', type is buried
_LC031 = TFFE( _EQ049, _EQ050, !clearxianshi, VCC, VCC);
_EQ049 = bego & _LC022 & !_LC023 & !_LC028 & _LC031
# bego & _LC022 & _LC023 & _LC028;
_EQ050 = !_LC034 & !_LC035 & _LC036;
-- Node name is '|XIANSHI:20|qiduanyima:g1|~360~1'
-- Equation name is '_LC059', type is buried
-- synthesized logic cell
_LC059 = LCELL( _EQ051 $ GND);
_EQ051 = !_LC023 & !_LC028 & !_LC031 & _LC060 & you
# !_LC054 & _LC060 & !_LC061 & !_LC063 & !you;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\bahe1\yima\baheyouxi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,409K
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