baheyouxi.rpt
来自「使用max_plus2在FPGA下实现拔河游戏机的功能」· RPT 代码 · 共 1,017 行 · 第 1/4 页
RPT
1,017 行
baheyouxi
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
7 8 A OUTPUT t 0 0 0 0 0 0 0 di
21 17 B OUTPUT t 0 0 0 0 3 0 0 q0
4 16 A OUTPUT t 0 0 0 0 3 0 0 q1
27 37 C OUTPUT t 0 0 0 0 4 0 0 q2
12 1 A OUTPUT t 0 0 0 0 3 0 0 q3
19 20 B OUTPUT t 0 0 0 0 4 0 0 q4
18 21 B OUTPUT t 0 0 0 0 4 0 0 q5
16 25 B OUTPUT t 0 0 0 0 4 0 0 q6
6 11 A OUTPUT t 0 0 0 0 3 0 0 q7
17 24 B OUTPUT t 0 0 0 0 4 0 0 q8
20 19 B OUTPUT t 0 0 0 0 4 0 0 q9
13 32 B OUTPUT t 0 0 0 0 4 0 0 q10
14 30 B OUTPUT t 0 0 0 0 4 0 0 q11
8 5 A OUTPUT t 0 0 0 0 4 0 0 q12
9 4 A OUTPUT t 0 0 0 0 4 0 0 q13
11 3 A OUTPUT t 0 0 0 0 4 0 0 q14
5 14 A FF t 0 0 0 1 0 5 5 you (|XIANSHI:20|jishu2:d1|:4)
36 52 D OUTPUT t 1 1 0 0 11 0 0 y0
37 53 D OUTPUT t 1 1 0 0 5 0 0 y1
38 56 D OUTPUT t 1 1 0 0 5 0 0 y2
41 64 D OUTPUT t 1 1 0 0 11 0 0 y3
40 62 D OUTPUT t 2 1 1 0 11 0 0 y4
34 51 D OUTPUT t 1 1 0 0 11 0 0 y5
33 49 D OUTPUT t 2 1 0 0 5 0 0 y6
39 57 D FF t ! 0 0 0 1 1 0 0 zuo (|XIANSHI:20|jishu2:d1|~4~1)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\bahe1\yima\baheyouxi.rpt
baheyouxi
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 18 B SOFT t 0 0 0 0 4 0 10 |HEXIN:26|yima:g1|:1651
- 43 C DFFE + t 1 1 0 1 6 0 4 |HEXIN:26|zonghejishu:u1|dchufa:i1|:3
- 27 B SOFT t 0 0 0 0 2 0 1 |HEXIN:26|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|addcore:adder0|gcp2
(26) 36 C TFFE t 0 0 0 1 7 14 11 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp3 (|HEXIN:26|zonghejishu:u1|jishu16:g1|:8)
(25) 35 C TFFE t 3 3 0 2 9 14 13 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp2 (|HEXIN:26|zonghejishu:u1|jishu16:g1|:9)
- 34 C TFFE t 3 3 0 2 9 14 13 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp1 (|HEXIN:26|zonghejishu:u1|jishu16:g1|:10)
(24) 33 C TFFE t 3 3 0 2 7 14 4 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp0 (|HEXIN:26|zonghejishu:u1|jishu16:g1|:11)
- 39 C TFFE + t 1 1 0 1 7 0 4 |HEXIN:26|zonghejishu:u1|jkslect:u1|jout (|HEXIN:26|zonghejishu:u1|jkslect:u1|:5)
(28) 40 C SOFT s t 1 1 0 1 6 0 1 |HEXIN:26|zonghejishu:u1|~60~1
- 26 B DFFE + t 0 0 0 1 0 0 2 |JICUNQI:27|dchufa:u1|:3
- 9 A DFFE + t 0 0 0 0 1 0 2 |JICUNQI:27|dchufa:u2|:3
(29) 41 C DFFE + t 0 0 0 0 1 0 2 |JICUNQI:27|dchufa:u3|:3
- 44 C DFFE + t 0 0 0 0 1 0 1 |JICUNQI:27|dchufa:u4|:3
(32) 48 C LCELL s t 1 0 1 1 5 0 7 |JICUNQI:27|~112~1
- 29 B DFFE + t 0 0 0 1 0 0 2 |JICUNQI:28|dchufa:u1|:3
(31) 46 C DFFE + t 0 0 0 0 1 0 2 |JICUNQI:28|dchufa:u2|:3
- 45 C DFFE + t 0 0 0 0 1 0 2 |JICUNQI:28|dchufa:u3|:3
- 42 C DFFE + t 0 0 0 0 1 0 1 |JICUNQI:28|dchufa:u4|:3
- 38 C LCELL s t 1 0 1 1 5 0 7 |JICUNQI:28|~112~1
- 55 D LCELL s t 0 0 0 0 3 7 0 |XIANSHI:20|duolufuyong:w1|~328~1
- 50 D LCELL s t 0 0 0 0 3 7 0 |XIANSHI:20|duolufuyong:w1|~337~1
- 58 D LCELL s t 0 0 0 0 3 7 0 |XIANSHI:20|duolufuyong:w1|~346~1
- 60 D LCELL s t 0 0 0 0 3 7 1 |XIANSHI:20|duolufuyong:w1|~355~1
- 61 D TFFE t 0 0 0 2 5 4 4 |XIANSHI:20|jishu10:k1|count3 (|XIANSHI:20|jishu10:k1|:8)
- 54 D TFFE t 0 0 0 2 3 4 4 |XIANSHI:20|jishu10:k1|count2 (|XIANSHI:20|jishu10:k1|:9)
- 63 D TFFE t 1 0 1 2 5 4 5 |XIANSHI:20|jishu10:k1|count1 (|XIANSHI:20|jishu10:k1|:10)
- 47 C TFFE t 0 0 0 2 1 0 4 |XIANSHI:20|jishu10:k1|count0 (|XIANSHI:20|jishu10:k1|:11)
- 31 B TFFE t 0 0 0 2 7 4 4 |XIANSHI:20|jishu10:k2|count3 (|XIANSHI:20|jishu10:k2|:8)
- 28 B TFFE t 0 0 0 2 5 4 4 |XIANSHI:20|jishu10:k2|count2 (|XIANSHI:20|jishu10:k2|:9)
- 23 B TFFE t 1 0 1 2 7 4 5 |XIANSHI:20|jishu10:k2|count1 (|XIANSHI:20|jishu10:k2|:10)
- 22 B TFFE t 0 0 0 2 3 0 4 |XIANSHI:20|jishu10:k2|count0 (|XIANSHI:20|jishu10:k2|:11)
- 59 D SOFT s t 0 0 0 0 8 3 0 |XIANSHI:20|qiduanyima:g1|~360~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\bahe1\yima\baheyouxi.rpt
baheyouxi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------------- LC8 di
| +--------------- LC9 |JICUNQI:27|dchufa:u2|:3
| | +------------- LC16 q1
| | | +----------- LC1 q3
| | | | +--------- LC11 q7
| | | | | +------- LC5 q12
| | | | | | +----- LC4 q13
| | | | | | | +--- LC3 q14
| | | | | | | | +- LC14 you
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
Pin
26 -> - - - - - - - - * | * - - * | <-- clk1
43 -> - - - - - - - - - | - - - - | <-- cp
LC36 -> - - * * - * * * - | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp3
LC35 -> - - * - * * * * - | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp2
LC34 -> - - - * * * * * - | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp1
LC33 -> - - * * * * * * - | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp0
LC26 -> - * - - - - - - - | * - * - | <-- |JICUNQI:27|dchufa:u1|:3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\bahe1\yima\baheyouxi.rpt
baheyouxi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC18 |HEXIN:26|yima:g1|:1651
| +----------------------------- LC27 |HEXIN:26|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|addcore:adder0|gcp2
| | +--------------------------- LC26 |JICUNQI:27|dchufa:u1|:3
| | | +------------------------- LC29 |JICUNQI:28|dchufa:u1|:3
| | | | +----------------------- LC17 q0
| | | | | +--------------------- LC20 q4
| | | | | | +------------------- LC21 q5
| | | | | | | +----------------- LC25 q6
| | | | | | | | +--------------- LC24 q8
| | | | | | | | | +------------- LC19 q9
| | | | | | | | | | +----------- LC32 q10
| | | | | | | | | | | +--------- LC30 q11
| | | | | | | | | | | | +------- LC31 |XIANSHI:20|jishu10:k2|count3
| | | | | | | | | | | | | +----- LC28 |XIANSHI:20|jishu10:k2|count2
| | | | | | | | | | | | | | +--- LC23 |XIANSHI:20|jishu10:k2|count1
| | | | | | | | | | | | | | | +- LC22 |XIANSHI:20|jishu10:k2|count0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC31 -> - - - - - - - - - - - - * - * - | - * - * | <-- |XIANSHI:20|jishu10:k2|count3
LC28 -> - - - - - - - - - - - - * * * - | - * - * | <-- |XIANSHI:20|jishu10:k2|count2
LC23 -> - - - - - - - - - - - - * * * - | - * - * | <-- |XIANSHI:20|jishu10:k2|count1
LC22 -> - - - - - - - - - - - - * * * * | - * - * | <-- |XIANSHI:20|jishu10:k2|count0
Pin
29 -> - - - - - - - - - - - - * * * * | - * * * | <-- bego
25 -> - - - - - - - - - - - - * * * * | - * * * | <-- clearxianshi
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- cp
28 -> - - * - - - - - - - - - - - - - | - * - - | <-- left
24 -> - - - * - - - - - - - - - - - - | - * - - | <-- right
LC36 -> * - - - * * * * * * * * * * * * | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp3
LC35 -> * * - - * * * * * * * * * * * * | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp2
LC34 -> * * - - * * * * * * * * * * * * | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp1
LC33 -> * - - - - * * * * * * * - - - - | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\bahe1\yima\baheyouxi.rpt
baheyouxi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC43 |HEXIN:26|zonghejishu:u1|dchufa:i1|:3
| +----------------------------- LC36 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp3
| | +--------------------------- LC35 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp2
| | | +------------------------- LC34 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp1
| | | | +----------------------- LC33 |HEXIN:26|zonghejishu:u1|jishu16:g1|temp0
| | | | | +--------------------- LC39 |HEXIN:26|zonghejishu:u1|jkslect:u1|jout
| | | | | | +------------------- LC40 |HEXIN:26|zonghejishu:u1|~60~1
| | | | | | | +----------------- LC41 |JICUNQI:27|dchufa:u3|:3
| | | | | | | | +--------------- LC44 |JICUNQI:27|dchufa:u4|:3
| | | | | | | | | +------------- LC48 |JICUNQI:27|~112~1
| | | | | | | | | | +----------- LC46 |JICUNQI:28|dchufa:u2|:3
| | | | | | | | | | | +--------- LC45 |JICUNQI:28|dchufa:u3|:3
| | | | | | | | | | | | +------- LC42 |JICUNQI:28|dchufa:u4|:3
| | | | | | | | | | | | | +----- LC38 |JICUNQI:28|~112~1
| | | | | | | | | | | | | | +--- LC37 q2
| | | | | | | | | | | | | | | +- LC47 |XIANSHI:20|jishu10:k1|count0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC43 -> - * * * * - - - - - - - - - - - | - - * - | <-- |HEXIN:26|zonghejishu:u1|dchufa:i1|:3
LC36 -> * * * * * * * - - - - - - - * - | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp3
LC35 -> * * * * * * * - - - - - - - * - | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp2
LC34 -> * * * * * * * - - - - - - - * - | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp1
LC33 -> - * * * * - - - - - - - - - * - | * * * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|temp0
LC39 -> - * * * - * - - - - - - - - - - | - - * - | <-- |HEXIN:26|zonghejishu:u1|jkslect:u1|jout
LC40 -> - * - - - - - - - - - - - - - - | - - * - | <-- |HEXIN:26|zonghejishu:u1|~60~1
LC41 -> - - - - - - - - * * - - - - - - | - - * - | <-- |JICUNQI:27|dchufa:u3|:3
LC44 -> - - - - - - - - - * - - - - - - | - - * - | <-- |JICUNQI:27|dchufa:u4|:3
LC48 -> * - * * * * * - - * - - - - - - | - - * - | <-- |JICUNQI:27|~112~1
LC46 -> - - - - - - - - - - - * - * - - | - - * - | <-- |JICUNQI:28|dchufa:u2|:3
LC45 -> - - - - - - - - - - - - * * - - | - - * - | <-- |JICUNQI:28|dchufa:u3|:3
LC42 -> - - - - - - - - - - - - - * - - | - - * - | <-- |JICUNQI:28|dchufa:u4|:3
LC38 -> * - * * * * * - - - - - - * - - | - - * - | <-- |JICUNQI:28|~112~1
Pin
29 -> * - * * * * * - - * - - - * - * | - * * * | <-- bego
31 -> - * * * * - - - - - - - - - - - | - - * - | <-- clearhexin
25 -> - - - - - - - - - - - - - - - * | - * * * | <-- clearxianshi
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- cp
LC18 -> * - * * * * * - - - - - - - - * | - - * * | <-- |HEXIN:26|yima:g1|:1651
LC27 -> - * - - - - - - - - - - - - - - | - - * - | <-- |HEXIN:26|zonghejishu:u1|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|addcore:adder0|gcp2
LC26 -> - - - - - - - - - * - - - - - - | * - * - | <-- |JICUNQI:27|dchufa:u1|:3
LC9 -> - - - - - - - * - * - - - - - - | - - * - | <-- |JICUNQI:27|dchufa:u2|:3
LC29 -> - - - - - - - - - - * - - * - - | - - * - | <-- |JICUNQI:28|dchufa:u1|:3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\bahe1\yima\baheyouxi.rpt
baheyouxi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC55 |XIANSHI:20|duolufuyong:w1|~328~1
| +----------------------------- LC50 |XIANSHI:20|duolufuyong:w1|~337~1
| | +--------------------------- LC58 |XIANSHI:20|duolufuyong:w1|~346~1
| | | +------------------------- LC60 |XIANSHI:20|duolufuyong:w1|~355~1
| | | | +----------------------- LC61 |XIANSHI:20|jishu10:k1|count3
| | | | | +--------------------- LC54 |XIANSHI:20|jishu10:k1|count2
| | | | | | +------------------- LC63 |XIANSHI:20|jishu10:k1|count1
| | | | | | | +----------------- LC59 |XIANSHI:20|qiduanyima:g1|~360~1
| | | | | | | | +--------------- LC52 y0
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