jkslect.vhd

来自「使用max_plus2在FPGA下实现拔河游戏机的功能」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;

entity jkslect is
port(j,k,cp:in std_logic;
          q:out std_logic);
end jkslect;

architecture rtl of jkslect is
signal jout:std_logic;
begin
q<=jout; 
 process(cp,j,k)
  begin
   if(cp'event and cp='1')then
     if(j='1')and(k='0')then
       jout<='1';
 
     elsif(j='0')and(k='1')then
       jout<='0';


     end if;
   end if;
 end process;
end rtl;