zonghejishu.vhd

来自「使用max_plus2在FPGA下实现拔河游戏机的功能」· VHDL 代码 · 共 50 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity zonghejishu is
port(bego,left,right,over,clear,cp:in std_logic;
                         --xp,dp,cpp:out std_logic;
                           a,b,c,d:out std_logic);
end zonghejishu;

architecture one of zonghejishu is
  
  component jkslect
   port(j,k,cp:in std_logic;
          q:out std_logic);
  end component;

  component jishu16
   port(clk,clr,input:std_logic;
     qa,qb,qc,qd:out std_logic);
  end component;

  component dchufa
   port(clk,d:in std_logic;
            q:out std_logic);
  end component;

signal ll,rr,coclk,cocp,jkq,dchufaq:std_logic;
begin
    ll<=left and bego and (not over);
    rr<=right and bego and (not over);
    process(ll,rr,coclk)
    begin
     if((ll='1' and rr='1') or (ll='0' and rr='0'))then
      coclk<=ll xor rr;
     else 
      coclk<='1';
     end if;
    end process;
    cocp<=dchufaq and coclk;
    u1:jkslect port map(ll,rr,cp,jkq);
    i1:dchufa  port map(cp,coclk,dchufaq);
    g1:jishu16 port map(cocp,clear,jkq,a,b,c,d); 
    --xp<=coclk;
    --dp<=dchufaq;
    --cpp<=cocp; 
end one;