jishu16.vhd

来自「使用max_plus2在FPGA下实现拔河游戏机的功能」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jishu16 is
port(clk,clr,input:std_logic;
     qa,qb,qc,qd:out std_logic);
end jishu16;

architecture rtl of jishu16 is
signal temp:std_logic_vector(3 downto 0);
begin 
qa<=temp(0);
qb<=temp(1);
qc<=temp(2);
qd<=temp(3);
  process(clr,clk)
  begin
   if(clr='1')then
    temp<="0000";
   elsif(clk'event and clk='1')then
    if(input='1')then
    temp<=temp+'1';
    elsif(input='0')then
       temp<=temp-'1';
       else 
       temp<=temp;
       end if;
    
   end if;
end process;
end rtl;