📄 lalala.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC30 y2
| +----------------------------- LC28 y4
| | +--------------------------- LC31 y5
| | | +------------------------- LC32 y6
| | | | +----------------------- LC26 y7
| | | | | +--------------------- LC21 y8
| | | | | | +------------------- LC22 y9
| | | | | | | +----------------- LC23 y10
| | | | | | | | +--------------- LC24 y11
| | | | | | | | | +------------- LC25 y12
| | | | | | | | | | +----------- LC27 |ZONGHEJISHU:30|dchufa:i1|:3
| | | | | | | | | | | +--------- LC17 |ZONGHEJISHU:30|jishu16:g1|temp3
| | | | | | | | | | | | +------- LC18 |ZONGHEJISHU:30|jishu16:g1|temp2
| | | | | | | | | | | | | +----- LC19 |ZONGHEJISHU:30|jishu16:g1|temp1
| | | | | | | | | | | | | | +--- LC20 |ZONGHEJISHU:30|jishu16:g1|temp0
| | | | | | | | | | | | | | | +- LC29 |ZONGHEJISHU:30|jkslect:u1|jout
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC27 -> - - - - - - - - - - - * * * * - | - * | <-- |ZONGHEJISHU:30|dchufa:i1|:3
LC17 -> * * * * - * * * * * - * - - - - | * * | <-- |ZONGHEJISHU:30|jishu16:g1|temp3
LC18 -> * * * * * * * * * * - * * - - - | * * | <-- |ZONGHEJISHU:30|jishu16:g1|temp2
LC19 -> * * * * * * * * * * - * * * - - | * * | <-- |ZONGHEJISHU:30|jishu16:g1|temp1
LC20 -> * * * * * * * * * * - * * * * - | * * | <-- |ZONGHEJISHU:30|jishu16:g1|temp0
LC29 -> - - - - - - - - - - - * * * - * | - * | <-- |ZONGHEJISHU:30|jkslect:u1|jout
Pin
4 -> - - - - - - - - - - - * * * * - | - * | <-- clear
43 -> - - - - - - - - - - - - - - - - | - - | <-- cp
5 -> - - - - - - - - - - * * * * * * | - * | <-- left
6 -> - - - - - - - - - - * * * * * * | - * | <-- right
LC8 -> - - - - - - - - - - - * - - - - | - * | <-- |ZONGHEJISHU:30|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|addcore:adder0|gcp2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\bahe1\yima\lalala.rpt
lalala
** EQUATIONS **
clear : INPUT;
cp : INPUT;
left : INPUT;
right : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', location is LC009, type is output.
y0 = LCELL( _EQ001 $ GND);
_EQ001 = _LC017 & !_LC018 & !_LC019;
-- Node name is 'y1'
-- Equation name is 'y1', location is LC007, type is output.
y1 = LCELL( _EQ002 $ GND);
_EQ002 = _LC017 & !_LC018 & !_LC020;
-- Node name is 'y2'
-- Equation name is 'y2', location is LC030, type is output.
y2 = LCELL( _EQ003 $ GND);
_EQ003 = _LC017 & !_LC018 & _LC019 & _LC020
# _LC017 & !_LC018 & !_LC019 & !_LC020;
-- Node name is 'y3'
-- Equation name is 'y3', location is LC006, type is output.
y3 = LCELL( _EQ004 $ GND);
_EQ004 = _LC017 & !_LC019 & !_LC020;
-- Node name is 'y4'
-- Equation name is 'y4', location is LC028, type is output.
y4 = LCELL( _EQ005 $ GND);
_EQ005 = _LC017 & _LC018 & !_LC019 & _LC020
# _LC017 & !_LC018 & !_LC019 & !_LC020;
-- Node name is 'y5'
-- Equation name is 'y5', location is LC031, type is output.
y5 = LCELL( _EQ006 $ GND);
_EQ006 = _LC017 & _LC018 & _LC019 & !_LC020
# _LC017 & !_LC018 & !_LC019 & !_LC020;
-- Node name is 'y6'
-- Equation name is 'y6', location is LC032, type is output.
y6 = LCELL( _EQ007 $ GND);
_EQ007 = _LC017 & _LC018 & _LC019 & _LC020
# _LC017 & !_LC018 & !_LC019 & !_LC020;
-- Node name is 'y7'
-- Equation name is 'y7', location is LC026, type is output.
y7 = LCELL( _EQ008 $ GND);
_EQ008 = !_LC018 & !_LC019 & !_LC020;
-- Node name is 'y8'
-- Equation name is 'y8', location is LC021, type is output.
y8 = LCELL( _EQ009 $ GND);
_EQ009 = _LC017 & !_LC018 & !_LC019 & !_LC020
# !_LC017 & !_LC018 & !_LC019 & _LC020;
-- Node name is 'y9'
-- Equation name is 'y9', location is LC022, type is output.
y9 = LCELL( _EQ010 $ GND);
_EQ010 = !_LC017 & !_LC018 & _LC019 & !_LC020
# _LC017 & !_LC018 & !_LC019 & !_LC020;
-- Node name is 'y10'
-- Equation name is 'y10', location is LC023, type is output.
y10 = LCELL( _EQ011 $ GND);
_EQ011 = !_LC017 & !_LC018 & _LC019 & _LC020
# _LC017 & !_LC018 & !_LC019 & !_LC020;
-- Node name is 'y11'
-- Equation name is 'y11', location is LC024, type is output.
y11 = LCELL( _EQ012 $ GND);
_EQ012 = _LC017 & !_LC018 & !_LC019 & !_LC020
# !_LC017 & _LC018 & !_LC019 & !_LC020;
-- Node name is 'y12'
-- Equation name is 'y12', location is LC025, type is output.
y12 = LCELL( _EQ013 $ GND);
_EQ013 = !_LC017 & _LC018 & !_LC019 & _LC020
# _LC017 & !_LC018 & !_LC019 & !_LC020;
-- Node name is 'y13'
-- Equation name is 'y13', location is LC004, type is output.
y13 = LCELL( _EQ014 $ GND);
_EQ014 = !_LC017 & _LC018 & _LC019 & !_LC020
# _LC017 & !_LC018 & !_LC019 & !_LC020;
-- Node name is 'y14'
-- Equation name is 'y14', location is LC005, type is output.
y14 = LCELL( _EQ015 $ GND);
_EQ015 = !_LC017 & _LC018 & _LC019 & _LC020
# _LC017 & !_LC018 & !_LC019 & !_LC020;
-- Node name is '|ZONGHEJISHU:30|dchufa:i1|:3'
-- Equation name is '_LC027', type is buried
_LC027 = DFFE( right $ left, GLOBAL( cp), VCC, VCC, VCC);
-- Node name is '|ZONGHEJISHU:30|jishu16:g1|LPM_ADD_SUB:79|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC008', type is buried
_LC008 = LCELL( _EQ016 $ _LC018);
_EQ016 = !_LC018 & _LC019;
-- Node name is '|ZONGHEJISHU:30|jishu16:g1|:11' = '|ZONGHEJISHU:30|jishu16:g1|temp0'
-- Equation name is '_LC020', type is buried
_LC020 = TFFE( VCC, _EQ017, !clear, VCC, VCC);
_EQ017 = _LC027 & _X001 & _X002;
_X001 = EXP(!left & !right);
_X002 = EXP( left & right);
-- Node name is '|ZONGHEJISHU:30|jishu16:g1|:10' = '|ZONGHEJISHU:30|jishu16:g1|temp1'
-- Equation name is '_LC019', type is buried
_LC019 = TFFE( _EQ018, _EQ019, !clear, VCC, VCC);
_EQ018 = _LC020 & _LC029
# !_LC020 & !_LC029;
_EQ019 = _LC027 & _X001 & _X002;
_X001 = EXP(!left & !right);
_X002 = EXP( left & right);
-- Node name is '|ZONGHEJISHU:30|jishu16:g1|:9' = '|ZONGHEJISHU:30|jishu16:g1|temp2'
-- Equation name is '_LC018', type is buried
_LC018 = TFFE( _EQ020, _EQ021, !clear, VCC, VCC);
_EQ020 = _LC019 & _LC020 & _LC029
# !_LC019 & !_LC020 & !_LC029;
_EQ021 = _LC027 & _X001 & _X002;
_X001 = EXP(!left & !right);
_X002 = EXP( left & right);
-- Node name is '|ZONGHEJISHU:30|jishu16:g1|:8' = '|ZONGHEJISHU:30|jishu16:g1|temp3'
-- Equation name is '_LC017', type is buried
_LC017 = TFFE( _EQ022, _EQ023, !clear, VCC, VCC);
_EQ022 = _LC018 & _LC019 & _LC020 & _LC029
# !_LC008 & !_LC020 & !_LC029;
_EQ023 = _LC027 & _X001 & _X002;
_X001 = EXP(!left & !right);
_X002 = EXP( left & right);
-- Node name is '|ZONGHEJISHU:30|jkslect:u1|:5' = '|ZONGHEJISHU:30|jkslect:u1|jout'
-- Equation name is '_LC029', type is buried
_LC029 = DFFE( _EQ024 $ left, GLOBAL( cp), VCC, VCC, VCC);
_EQ024 = !_LC029 & left & right
# _LC029 & !left & !right;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\bahe1\yima\lalala.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 7,834K
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