sim1.mdl

来自「卷积编码和译码全过程的MATLAB源代码」· MDL 代码 · 共 707 行 · 第 1/2 页

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	      GenerateComments	      on
	      IgnoreCustomStorageClasses on
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	      MaxIdLength	      31
	      PreserveName	      off
	      PreserveNameWithParent  off
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	      IncAutoGenComments      off
	      SimulinkDataObjDesc     off
	      SFDataObjDesc	      off
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	      PrefixModelToSubsysFcnNames on
	      CustomSymbolStr	      "$R$N$M"
	      MangleLength	      1
	      DefineNamingRule	      "None"
	      ParamNamingRule	      "None"
	      SignalNamingRule	      "None"
	      InsertBlockDesc	      off
	      SimulinkBlockComments   on
	      EnableCustomComments    off
	      InlinedPrmAccess	      "Literals"
	      ReqsInCode	      off
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	    Simulink.GRTTargetCC {
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	      Array {
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		Cell			"IncludeMdlTerminateFcn"
		Cell			"CombineOutputUpdateFcns"
		Cell			"SuppressErrorStatus"
		Cell			"ERTCustomFileBanners"
		Cell			"GenerateSampleERTMain"
		Cell			"MultiInstanceERTCode"
		Cell			"PurelyIntegerCode"
		Cell			"SupportNonFinite"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		PropName		"DisabledProps"
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	      Version		      "1.1.0"
	      TargetFcnLib	      "ansi_tfl_tmw.mat"
	      TargetLibSuffix	      ""
	      TargetPreCompLibLocation ""
	      GenFloatMathFcnCalls    "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
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	      LogVarNameModifier      "rt_"
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	      SupportContinuousTime   on
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	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
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	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
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	    PropName		    "Components"
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	PropName		"Components"
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      Name		      "Configuration"
      SimulationMode	      "normal"
      CurrentDlgPage	      "Solver"
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    PropName		    "ConfigurationSets"
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    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "arial"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
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  BlockParameterDefaults {
    Block {
      BlockType		      Inport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      LatchByDelayingOutsideSignal off
      LatchByCopyingInsideSignal off
      Interpolate	      on
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    Block {
      BlockType		      Logic
      Operator		      "AND"
      Inputs		      "2"
      AllPortsSameDT	      on
      OutDataTypeMode	      "Logical (see Configuration Parameters: Optimiza"
"tion)"
      LogicDataType	      "uint(8)"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Memory
      X0		      "0"
      InheritSampleTime	      off
      LinearizeMemory	      off
      StateMustResolveToSignalObject off
      RTWStateStorageClass    "Auto"
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    Block {
      BlockType		      Outport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
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      PortDimensions	      "-1"
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      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
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    HorizontalAlignment	    "center"
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    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "arial"
    FontSize		    10
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    FontName		    "arial"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
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    Name		    "sim1"
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    ModelBrowserWidth	    200
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      IconDisplay	      "Port number"
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      Name		      "Logical\nOperator"
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      Position		      [125, 182, 155, 213]
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      Name		      "Logical\nOperator1"
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      Position		      [285, 177, 315, 208]
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      OutDataTypeMode	      "Boolean"
    }
    Block {
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      Name		      "Logical\nOperator2"
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      Position		      [460, 169, 490, 201]
      Operator		      "XOR"
      Inputs		      "3"
      AllPortsSameDT	      off
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      BlockType		      Outport
      Name		      "Out3"
      Position		      [540, 178, 570, 192]
      Port		      "3"
      IconDisplay	      "Port number"
      BusOutputAsStruct	      off
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      SrcBlock		      "Memory"
      SrcPort		      1
      Points		      [35, 0]
      DstBlock		      "Logical\nOperator1"
      DstPort		      2
    }
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      SrcBlock		      "Logical\nOperator1"
      SrcPort		      1
      Points		      [0, 0]
      DstBlock		      "Memory1"
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      SrcBlock		      "Memory1"
      SrcPort		      1
      Points		      [60, 0]
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      DstPort		      3
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      SrcBlock		      "Logical\nOperator2"
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      Points		      [30, 0]
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	DstBlock		"Logical\nOperator"
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}