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📄 sim1.mdl

📁 卷积编码和译码全过程的MATLAB源代码
💻 MDL
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	      Version		      "1.1.0"
	      ForceParamTrailComments off
	      GenerateComments	      on
	      IgnoreCustomStorageClasses on
	      IncHierarchyInIds	      off
	      MaxIdLength	      31
	      PreserveName	      off
	      PreserveNameWithParent  off
	      ShowEliminatedStatement off
	      IncAutoGenComments      off
	      SimulinkDataObjDesc     off
	      SFDataObjDesc	      off
	      IncDataTypeInIds	      off
	      PrefixModelToSubsysFcnNames on
	      CustomSymbolStr	      "$R$N$M"
	      MangleLength	      1
	      DefineNamingRule	      "None"
	      ParamNamingRule	      "None"
	      SignalNamingRule	      "None"
	      InsertBlockDesc	      off
	      SimulinkBlockComments   on
	      EnableCustomComments    off
	      InlinedPrmAccess	      "Literals"
	      ReqsInCode	      off
	    }
	    Simulink.GRTTargetCC {
	      $BackupClass	      "Simulink.TargetCC"
	      $ObjectID		      10
	      Array {
		Type			"Cell"
		Dimension		12
		Cell			"IncludeMdlTerminateFcn"
		Cell			"CombineOutputUpdateFcns"
		Cell			"SuppressErrorStatus"
		Cell			"ERTCustomFileBanners"
		Cell			"GenerateSampleERTMain"
		Cell			"MultiInstanceERTCode"
		Cell			"PurelyIntegerCode"
		Cell			"SupportNonFinite"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		PropName		"DisabledProps"
	      }
	      Version		      "1.1.0"
	      TargetFcnLib	      "ansi_tfl_tmw.mat"
	      TargetLibSuffix	      ""
	      TargetPreCompLibLocation ""
	      GenFloatMathFcnCalls    "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
	      GenerateSampleERTMain   off
	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      IncludeMdlTerminateFcn  on
	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      SimulationMode	      "normal"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "arial"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Inport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      LatchByDelayingOutsideSignal off
      LatchByCopyingInsideSignal off
      Interpolate	      on
    }
    Block {
      BlockType		      Logic
      Operator		      "AND"
      Inputs		      "2"
      AllPortsSameDT	      on
      OutDataTypeMode	      "Logical (see Configuration Parameters: Optimiza"
"tion)"
      LogicDataType	      "uint(8)"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Memory
      X0		      "0"
      InheritSampleTime	      off
      LinearizeMemory	      off
      StateMustResolveToSignalObject off
      RTWStateStorageClass    "Auto"
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "arial"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "arial"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "sim1"
    Location		    [2, 82, 1022, 716]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Inport
      Name		      "In1"
      Position		      [45, 58, 75, 72]
      IconDisplay	      "Port number"
    }
    Block {
      BlockType		      Inport
      Name		      "In2"
      Position		      [45, 118, 75, 132]
      Port		      "2"
      IconDisplay	      "Port number"
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator"
      Ports		      [2, 1]
      Position		      [125, 182, 155, 213]
      Operator		      "XOR"
      AllPortsSameDT	      off
      OutDataTypeMode	      "Boolean"
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator1"
      Ports		      [2, 1]
      Position		      [285, 177, 315, 208]
      Operator		      "XOR"
      AllPortsSameDT	      off
      OutDataTypeMode	      "Boolean"
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator2"
      Ports		      [3, 1]
      Position		      [460, 169, 490, 201]
      Operator		      "XOR"
      Inputs		      "3"
      AllPortsSameDT	      off
      OutDataTypeMode	      "Boolean"
    }
    Block {
      BlockType		      Memory
      Name		      "Memory"
      Position		      [200, 185, 230, 215]
    }
    Block {
      BlockType		      Memory
      Name		      "Memory1"
      Position		      [350, 180, 380, 210]
    }
    Block {
      BlockType		      Outport
      Name		      "Out1"
      Position		      [540, 58, 570, 72]
      IconDisplay	      "Port number"
      BusOutputAsStruct	      off
    }
    Block {
      BlockType		      Outport
      Name		      "Out2"
      Position		      [540, 118, 570, 132]
      Port		      "2"
      IconDisplay	      "Port number"
      BusOutputAsStruct	      off
    }
    Block {
      BlockType		      Outport
      Name		      "Out3"
      Position		      [540, 178, 570, 192]
      Port		      "3"
      IconDisplay	      "Port number"
      BusOutputAsStruct	      off
    }
    Line {
      SrcBlock		      "Logical\nOperator"
      SrcPort		      1
      Points		      [0, 0]
      DstBlock		      "Memory"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Memory"
      SrcPort		      1
      Points		      [35, 0]
      DstBlock		      "Logical\nOperator1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Logical\nOperator1"
      SrcPort		      1
      Points		      [0, 0]
      DstBlock		      "Memory1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Memory1"
      SrcPort		      1
      Points		      [60, 0]
      DstBlock		      "Logical\nOperator2"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Logical\nOperator2"
      SrcPort		      1
      Points		      [0, 0]
      DstBlock		      "Out3"
      DstPort		      1
    }
    Line {
      SrcBlock		      "In1"
      SrcPort		      1
      Points		      [30, 0]
      Branch {
	DstBlock		"Logical\nOperator"
	DstPort			1
      }
      Branch {
	Points			[140, 0]
	Branch {
	  Points		  [0, 120]
	  DstBlock		  "Logical\nOperator1"
	  DstPort		  1
	}
	Branch {
	  Points		  [185, 0]
	  Branch {
	    DstBlock		    "Out1"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110]
	    DstBlock		    "Logical\nOperator2"
	    DstPort		    1
	  }
	}
      }
    }
    Line {
      SrcBlock		      "In2"
      SrcPort		      1
      Points		      [10, 0]
      Branch {
	Points			[0, 80]
	DstBlock		"Logical\nOperator"
	DstPort			2
      }
      Branch {
	Points			[330, 0]
	Branch {
	  DstBlock		  "Out2"
	  DstPort		  1
	}
	Branch {
	  Points		  [0, 60]
	  DstBlock		  "Logical\nOperator2"
	  DstPort		  2
	}
      }
    }
  }
}

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