📄 sd.lis
字号:
00F8 L26:
00F8 1601 movw R2,R12
00FA 2A20 and R2,R10
00FC 3B20 and R3,R11
00FE 2220 tst R2
0100 29F7 brne L20
0102 3320 tst R3
0104 19F7 brne L20
0106 X0:
0106 .dbline 96
0106 ; {
0106 ; tmp=Read_Byte_SD();
0106 ; }
0106 ; //SD_Disable();
0106 ; return(tmp);
0106 062F mov R16,R22
0108 .dbline -2
0108 L19:
0108 0E940000 xcall pop_gset4
010C 2296 adiw R28,2
010E .dbline 0 ; func end
010E 0895 ret
0110 .dbsym r Timeout 20 c
0110 .dbsym r tmp 22 c
0110 .dbsym l address 8 l
0110 .dbsym r CMD 22 c
0110 .dbend
.area lit(rom, con, rel)
0000 L28:
0000 4000 .byte 64,0
0002 0000 .byte 0,0
0004 0095 .byte 0,149
.area text(rom, con, rel)
0110 .dbfile E:\MYWORK~1\开发设计\AVR-MP3\mp3开发板光盘\驱动程序\MP3BOA~1.8\SD.c
0110 .dbfunc e SDInit _SDInit fc
0110 ; b -> R10
0110 ; a -> R20
0110 ; retry -> R22
0110 ; CMD -> y+0
.even
0110 _SDInit::
0110 0E940000 xcall push_gset3
0114 2697 sbiw R28,6
0116 .dbline -1
0116 .dbline 101
0116 ; }
0116 ;
0116 ; //=======================================================================
0116 ; uint8 SDInit(void)
0116 ; {
0116 .dbline 103
0116 ; uint8 a,b,retry;
0116 ; uint8 CMD[]={0x40,0x00,0x00,0x00,0x00,0x95};
0116 80E0 ldi R24,<L28
0118 90E0 ldi R25,>L28
011A FE01 movw R30,R28
011C 06E0 ldi R16,6
011E 10E0 ldi R17,0
0120 FA93 st -y,R31
0122 EA93 st -y,R30
0124 9A93 st -y,R25
0126 8A93 st -y,R24
0128 0E940000 xcall asgncblk
012C .dbline 105
012C ;
012C ; asm("cli"); //clear all interrupt.
012C F894 cli
012E .dbline 108
012E ; // Set certain pins to inputs and others to outputs
012E ; // Only SPI_DI (data in) is an input
012E ; SD_Direction_REG&=~(1<<SPI_DI);
012E BE98 cbi 0x17,6
0130 .dbline 109
0130 ; SD_Direction_REG|=(1<<SPI_Clock);
0130 BF9A sbi 0x17,7
0132 .dbline 110
0132 ; SD_Direction_REG|=(1<<SPI_DO);
0132 BD9A sbi 0x17,5
0134 .dbline 111
0134 ; SD_Direction_REG|=(1<<SD_Chip_Select);
0134 BC9A sbi 0x17,4
0136 .dbline 112
0136 ; SD_Write|=(1<<SD_Chip_Select);
0136 C49A sbi 0x18,4
0138 .dbline 113
0138 ; SD_Write|=(1<<SPI_DI);
0138 C69A sbi 0x18,6
013A .dbline 116
013A ;
013A ; //We need to wait for the SD_Direction_REG to be ready
013A ; for(a=0;a<200;a++)
013A 4427 clr R20
013C 02C0 xjmp L32
013E L29:
013E .dbline 117
013E .dbline 118
013E 0000 nop
0140 .dbline 119
0140 L30:
0140 .dbline 116
0140 4395 inc R20
0142 L32:
0142 .dbline 116
0142 483C cpi R20,200
0144 E0F3 brlo L29
0146 .dbline 119
0146 ; {
0146 ; nop();
0146 ; };
0146 .dbline 121
0146 ; //Enable SPI in Master Mode with IDLE low and clock at 8M/128
0146 ; SPCR=(1<<SPE)|(1<<MSTR)|(1<<SPR0)|(1<<SPR1);
0146 83E5 ldi R24,83
0148 8DB9 out 0xd,R24
014A .dbline 122
014A ; SPSR&=~(1<<SPI2X);
014A 7098 cbi 0xe,0
014C .dbline 125
014C ;
014C ; // We need to give the card about a Hundred cycles to load
014C ; for (b=0;b<0x0f;++b)
014C AA24 clr R10
014E 03C0 xjmp L36
0150 L33:
0150 .dbline 126
0150 .dbline 127
0150 0FEF ldi R16,255
0152 5CDF xcall _Write_Byte_SD
0154 .dbline 128
0154 L34:
0154 .dbline 125
0154 A394 inc R10
0156 L36:
0156 .dbline 125
0156 8A2D mov R24,R10
0158 8F30 cpi R24,15
015A D0F3 brlo L33
015C .dbline 131
015C ; {
015C ; Write_Byte_SD(0xff);
015C ; }
015C ;
015C ; //Send the initialization commands to the card
015C ; retry=0;
015C 6627 clr R22
015E 0CC0 xjmp L38
0160 L37:
0160 .dbline 134
0160 ;
0160 ; while(Write_Command_SD1(CMD)!=0X01)
0160 ; {
0160 .dbline 135
0160 ; Delay_ms(10); //很重要，要不然就要REST才可以
0160 0AE0 ldi R16,10
0162 10E0 ldi R17,0
0164 0E940000 xcall _Delay_ms
0168 .dbline 137
0168 ; //fail and return
0168 ; if(retry++>50)
0168 262E mov R2,R22
016A 3324 clr R3
016C 6F5F subi R22,255 ; addi 1
016E 82E3 ldi R24,50
0170 8215 cp R24,R2
0172 10F4 brsh L40
0174 .dbline 138
0174 ; {
0174 .dbline 139
0174 ; return 1;
0174 01E0 ldi R16,1
0176 21C0 xjmp L27
0178 L40:
0178 .dbline 141
0178 L38:
0178 .dbline 133
0178 8E01 movw R16,R28
017A 4CDF xcall _Write_Command_SD1
017C 0130 cpi R16,1
017E 81F7 brne L37
0180 .dbline 144
0180 ; }
0180 ; }
0180 ;
0180 ; //Send the 2nd command
0180 ; retry=0;
0180 6627 clr R22
0182 .dbline 145
0182 ; CMD[0]=0x41;
0182 81E4 ldi R24,65
0184 8883 std y+0,R24
0186 .dbline 146
0186 ; CMD[5]=0xFF;
0186 8FEF ldi R24,255
0188 8D83 std y+5,R24
018A 0CC0 xjmp L44
018C L43:
018C .dbline 149
018C ;
018C ; while(Write_Command_SD1(CMD)!=0)
018C ; {
018C .dbline 150
018C ; Delay_ms(10);
018C 0AE0 ldi R16,10
018E 10E0 ldi R17,0
0190 0E940000 xcall _Delay_ms
0194 .dbline 151
0194 ; if (retry++>50)
0194 262E mov R2,R22
0196 3324 clr R3
0198 6F5F subi R22,255 ; addi 1
019A 82E3 ldi R24,50
019C 8215 cp R24,R2
019E 10F4 brsh L46
01A0 .dbline 152
01A0 ; {
01A0 .dbline 153
01A0 ; return 2;
01A0 02E0 ldi R16,2
01A2 0BC0 xjmp L27
01A4 L46:
01A4 .dbline 155
01A4 L44:
01A4 .dbline 148
01A4 8E01 movw R16,R28
01A6 36DF xcall _Write_Command_SD1
01A8 0023 tst R16
01AA 81F7 brne L43
01AC .dbline 158
01AC ; }
01AC ; }
01AC ;
01AC ; //Set the SPI bus to full speed 8M/2
01AC ; SPCR&=~((1<<SPR0)|(1<<SPR1));
01AC 8DB1 in R24,0xd
01AE 8C7F andi R24,252
01B0 8DB9 out 0xd,R24
01B2 .dbline 159
01B2 ; SPSR|=(1<<SPI2X);
01B2 709A sbi 0xe,0
01B4 .dbline 163
01B4 ;
01B4 ; //Raise Chip Select
01B4 ;
01B4 ; SD_Disable();
01B4 C49A sbi 0x18,4
01B6 .dbline 163
01B6 .dbline 164
01B6 ; asm("sei");
01B6 7894 sei
01B8 .dbline 165
01B8 ; return 0;
01B8 0027 clr R16
01BA .dbline -2
01BA L27:
01BA 2696 adiw R28,6
01BC 0E940000 xcall pop_gset3
01C0 .dbline 0 ; func end
01C0 0895 ret
01C2 .dbsym r b 10 c
01C2 .dbsym r a 20 c
01C2 .dbsym r retry 22 c
01C2 .dbsym l CMD 0 A[6:6]c
01C2 .dbend
01C2 .dbfunc e SD_set_length _SD_set_length fc
01C2 ; retry -> R20
01C2 ; length -> R22,R23
.even
01C2 _SD_set_length::
01C2 0E940000 xcall push_gset2
01C6 B801 movw R22,R16
01C8 2297 sbiw R28,2
01CA .dbline -1
01CA .dbline 170
01CA ; }
01CA ;
01CA ; //=======================================================================
01CA ; uint8 SD_set_length(uint16 length)
01CA ; {
01CA 08C0 xjmp L50
01CC L49:
01CC .dbline 175
01CC ; uint8 retry;
01CC ; //Command to set the block length;
01CC ;
01CC ; while(Write_Command_SD(0x50,length)!=0)
01CC ; {
01CC .dbline 176
01CC ; if (retry++>10)
01CC 242E mov R2,R20
01CE 3324 clr R3
01D0 4F5F subi R20,255 ; addi 1
01D2 8AE0 ldi R24,10
01D4 8215 cp R24,R2
01D6 10F4 brsh L52
01D8 .dbline 177
01D8 ; {
01D8 .dbline 178
01D8 ; return 1;
01D8 01E0 ldi R16,1
01DA 0CC0 xjmp L48
01DC L52:
01DC .dbline 180
01DC L50:
01DC .dbline 174
01DC 1B01 movw R2,R22
01DE 4424 clr R4
01E0 5524 clr R5
01E2 4882 std y+0,R4
01E4 5982 std y+1,R5
01E6 9101 movw R18,R2
01E8 00E5 ldi R16,80
01EA 38DF xcall _Write_Command_SD
01EC 0023 tst R16
01EE 71F7 brne L49
01F0 .dbline 181
01F0 ; }
01F0 ; }
01F0 ; SD_Disable();
01F0 C49A sbi 0x18,4
01F2 .dbline 181
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