cardmifare.lst

Source Code Source Code Source Code Source Code Source Code Source Code Source Code Source Code Sour

 364               	/* prologue: frame size=0 */
 365 0184 9F92      		push r9
 366 0186 AF92      		push r10
 367 0188 BF92      		push r11
 368 018a CF92      		push r12
 369 018c DF92      		push r13
 370 018e EF92      		push r14
 371 0190 FF92      		push r15
 372 0192 0F93      		push r16
 373 0194 1F93      		push r17
 374 0196 CF93      		push r28
 375 0198 DF93      		push r29
 376               	/* prologue end (size=11) */
 377               	.LVL17:
 378 019a 982E      		mov r9,r24
 379 019c 162F      		mov r17,r22
 380 019e 7A01      		movw r14,r20
 381               	.LM59:
 382 01a0 862F      		mov r24,r22
 383               	.LVL18:
 384 01a2 8695      		lsr r24
 385 01a4 8695      		lsr r24
 386 01a6 C82F      		mov r28,r24
 387 01a8 D0E0      		ldi r29,lo8(0)
 388 01aa CC0F      		lsl r28
 389 01ac DD1F      		rol r29
 390 01ae CC0F      		lsl r28
 391 01b0 DD1F      		rol r29
 392 01b2 2396      		adiw r28,3
 393 01b4 00E0      		ldi r16,lo8(0)
 394               	.LVL19:
 395 01b6 C62E      		mov r12,r22
 396 01b8 DD24      		clr r13
 397               	.LVL20:
 398 01ba 70E0      		ldi r23,lo8(bufTemp)
 399 01bc A72E      		mov r10,r23
 400 01be 70E0      		ldi r23,hi8(bufTemp)
 401 01c0 B72E      		mov r11,r23
 402               	.LVL21:
 403               	.L35:
 404               	.LM60:
 405 01c2 B701      		movw r22,r14
 406 01c4 812F      		mov r24,r17
 407 01c6 0E94 0000 		call Mf500PiccWrite
 408 01ca 8823      		tst r24
 409 01cc 01F4      		brne .L36
 410               	.LVL22:
 411               	.LM61:
 412 01ce CC16      		cp r12,r28
 413 01d0 DD06      		cpc r13,r29
 414 01d2 01F0      		breq .L38
 415               	.LVL23:
 416               	.LM62:
 417 01d4 9920      		tst r9
 418 01d6 01F0      		breq .L38
 419               	.LM63:
 420 01d8 B501      		movw r22,r10
 421 01da 812F      		mov r24,r17
 422 01dc 0E94 0000 		call Mf500PiccRead
 423 01e0 8823      		tst r24
 424 01e2 01F4      		brne .L36
 425               	.LVL24:
 426               	.LM64:
 427 01e4 40E1      		ldi r20,lo8(16)
 428 01e6 B701      		movw r22,r14
 429 01e8 C501      		movw r24,r10
 430 01ea 0E94 0000 		call verificaDati
 431 01ee 8823      		tst r24
 432 01f0 01F4      		brne .L38
 433               	.L36:
 434               	.LM65:
 435 01f2 6FEF      		ldi r22,lo8(-1)
 436 01f4 812F      		mov r24,r17
 437 01f6 0E94 0000 		call Mf500AtenticaSett
 438               	.LM66:
 439 01fa 0F5F      		subi r16,lo8(-(1))
 440               	.LM67:
 441 01fc 0230      		cpi r16,lo8(2)
 442 01fe 01F4      		brne .L35
 443 0200 80E0      		ldi r24,lo8(0)
 444 0202 90E0      		ldi r25,hi8(0)
 445 0204 00C0      		rjmp .L43
 446               	.LVL25:
 447               	.L38:
 448 0206 8FEF      		ldi r24,lo8(255)
 449 0208 90E0      		ldi r25,hi8(255)
 450               	.L43:
 451               	/* epilogue: frame size=0 */
 452 020a DF91      		pop r29
 453 020c CF91      		pop r28
 454 020e 1F91      		pop r17
 455 0210 0F91      		pop r16
 456 0212 FF90      		pop r15
 457 0214 EF90      		pop r14
 458 0216 DF90      		pop r13
 459 0218 CF90      		pop r12
 460 021a BF90      		pop r11
 461 021c AF90      		pop r10
 462 021e 9F90      		pop r9
 463 0220 0895      		ret
 464               	/* epilogue end (size=12) */
 465               	/* function gesWriteChipRfid size 79 (56) */
 466               	.LFE21:
 468               	.global	readBlockRfid
 470               	readBlockRfid:
 471               	.LFB19:
 472               	.LM68:
 473               	/* prologue: frame size=0 */
 474 0222 1F93      		push r17
 475               	/* prologue end (size=1) */
 476               	.LVL26:
 477 0224 182F      		mov r17,r24
 478               	.LM69:
 479 0226 8034      		cpi r24,lo8(64)
 480 0228 00F4      		brsh .L48
 481               	.LM70:
 482 022a 682F      		mov r22,r24
 483 022c 8091 0000 		lds r24,sectorAutenticato
 484               	.LVL27:
 485 0230 0E94 0000 		call Mf500bloccoInSettore
 486               	.LVL28:
 487 0234 8823      		tst r24
 488 0236 01F4      		brne .L50
 489               	.LM71:
 490 0238 6091 0000 		lds r22,statoChip
 491 023c 812F      		mov r24,r17
 492 023e 0E94 0000 		call Mf500AtenticaSett
 493 0242 8823      		tst r24
 494 0244 01F0      		breq .L48
 495               	.L50:
 496               	.LM72:
 497 0246 60E0      		ldi r22,lo8(bufMifare)
 498 0248 70E0      		ldi r23,hi8(bufMifare)
 499 024a 812F      		mov r24,r17
 500 024c 0E94 0000 		call Mf500PiccRead
 501 0250 8823      		tst r24
 502 0252 01F4      		brne .L48
 503 0254 8FEF      		ldi r24,lo8(255)
 504 0256 90E0      		ldi r25,hi8(255)
 505 0258 00C0      		rjmp .L53
 506               	.LVL29:
 507               	.L48:
 508 025a 80E0      		ldi r24,lo8(0)
 509 025c 90E0      		ldi r25,hi8(0)
 510               	.L53:
 511               	/* epilogue: frame size=0 */
 512 025e 1F91      		pop r17
 513 0260 0895      		ret
 514               	/* epilogue end (size=2) */
 515               	/* function readBlockRfid size 32 (29) */
 516               	.LFE19:
 518               	.global	XponderWriteWord
 520               	XponderWriteWord:
 521               	.LFB29:
 522               	.LM73:
 523               	/* prologue: frame size=2 */
 524 0262 1F93      		push r17
 525 0264 CF93      		push r28
 526 0266 DF93      		push r29
 527 0268 CDB7      		in r28,__SP_L__
 528 026a DEB7      		in r29,__SP_H__
 529 026c 2297      		sbiw r28,2
 530 026e 0FB6      		in __tmp_reg__,__SREG__
 531 0270 F894      		cli
 532 0272 DEBF      		out __SP_H__,r29
 533 0274 0FBE      		out __SREG__,__tmp_reg__
 534 0276 CDBF      		out __SP_L__,r28
 535               	/* prologue end (size=11) */
 536               	.LVL30:
 537 0278 182F      		mov r17,r24
 538 027a 7A83      		std Y+2,r23
 539 027c 6983      		std Y+1,r22
 540               	.LM74:
 541 027e 8C50      		subi r24,lo8(-(-12))
 542               	.LVL31:
 543 0280 8437      		cpi r24,lo8(116)
 544 0282 00F0      		brlo .+2
 545 0284 00C0      		rjmp .L70
 546               	.LVL32:
 547               	.LM75:
 548 0286 8FEF      		ldi r24,lo8(-1)
 549 0288 8093 0000 		sts sectorAutenticato,r24
 550               	.LM76:
 551 028c 0E94 0000 		call Mf500WakeUpMode
 552               	.LBB12:
 553               	.LBB13:
 554               	.LBB14:
 555               	.LBB15:
 556               	.LM77:
 557 0290 89E9      		ldi r24,lo8(5529)
 558 0292 95E1      		ldi r25,hi8(5529)
 559               	.LVL33:
 560               	/* #APP */
 561 0294 0197      		1: sbiw r24,1
 562 0296 01F4      		brne 1b
 563               	/* #NOAPP */
 564               	.LBE15:
 565               	.LBE14:
 566               	.LBE13:
 567               	.LBE12:
 568               	.LM78:
 569 0298 81E0      		ldi r24,lo8(1)
 570               	.LVL34:
 571 029a 0E94 0000 		call readBlockRfid
 572 029e 8823      		tst r24
 573 02a0 01F0      		breq .L65
 574               	.LM79:
 575 02a2 2091 0000 		lds r18,bufMifare+15
 576 02a6 8091 0000 		lds r24,bufMifare+14
 577 02aa 820F      		add r24,r18
 578 02ac 912D      		mov r25,__zero_reg__
 579 02ae 911D      		adc r25,__zero_reg__
 580 02b0 8F3F      		cpi r24,255
 581 02b2 9105      		cpc r25,__zero_reg__
 582 02b4 01F4      		brne .L61
 583 02b6 2C30      		cpi r18,lo8(12)
 584 02b8 00F4      		brsh .L61
 585               	.LM80:
 586 02ba 2E5F      		subi r18,lo8(-(2))
 587 02bc 2093 0000 		sts offsetSectTra,r18
 588 02c0 00C0      		rjmp .L64
 589               	.L61:
 590               	.LM81:
 591 02c2 82E0      		ldi r24,lo8(2)
 592 02c4 8093 0000 		sts offsetSectTra,r24
 593               	.L64:
 594               	.LM82:
 595 02c8 812F      		mov r24,r17
 596 02ca 0E94 0000 		call getSecBlkByte
 597 02ce 8130      		cpi r24,lo8(1)
 598 02d0 01F4      		brne .L65
 599               	.LM83:
 600 02d2 8091 0000 		lds r24,bufAddress+1
 601 02d6 0E94 0000 		call readBlockRfid
 602 02da 8823      		tst r24
 603 02dc 01F0      		breq .L65
 604               	.LM84:
 605 02de E091 0000 		lds r30,bufAddress+3
 606 02e2 F0E0      		ldi r31,lo8(0)
 607 02e4 E050      		subi r30,lo8(-(bufMifare))
 608 02e6 F040      		sbci r31,hi8(-(bufMifare))
 609 02e8 8981      		ldd r24,Y+1
 610 02ea 9A81      		ldd r25,Y+2
 611 02ec 9183      		std Z+1,r25
 612 02ee 8083      		st Z,r24
 613               	.LM85:
 614 02f0 40E0      		ldi r20,lo8(bufMifare)
 615 02f2 50E0      		ldi r21,hi8(bufMifare)
 616 02f4 6091 0000 		lds r22,bufAddress+1
 617 02f8 80E0      		ldi r24,lo8(0)
 618 02fa 0E94 0000 		call gesWriteChipRfid
 619 02fe 8823      		tst r24
 620 0300 01F0      		breq .L65
 621               	.LM86:
 622 0302 0E94 0000 		call Mf500StandbyMode
 623 0306 80E0      		ldi r24,lo8(0)
 624 0308 90E0      		ldi r25,hi8(0)
 625 030a 00C0      		rjmp .L58
 626               	.L65:
 627               	.LM87:
 628 030c 0E94 0000 		call Mf500StandbyMode
 629               	.LVL35:
 630               	.L70:
 631 0310 81E0      		ldi r24,lo8(1)
 632 0312 90E0      		ldi r25,hi8(1)
 633               	.L58:
 634               	/* epilogue: frame size=2 */
 635 0314 2296      		adiw r28,2
 636 0316 0FB6      		in __tmp_reg__,__SREG__
 637 0318 F894      		cli
 638 031a DEBF      		out __SP_H__,r29
 639 031c 0FBE      		out __SREG__,__tmp_reg__
 640 031e CDBF      		out __SP_L__,r28
 641 0320 DF91      		pop r29
 642 0322 CF91      		pop r28
 643 0324 1F91      		pop r17
 644 0326 0895      		ret
 645               	/* epilogue end (size=10) */
 646               	/* function XponderWriteWord size 101 (80) */
 647               	.LFE29:
 649               	.global	__vector_3
 651               	__vector_3:
 652               	.LFB15:
 653               	.LM88:
 654               	/* prologue: frame size=0 */
 655 0328 1F92      		push __zero_reg__
 656 032a 0F92      		push __tmp_reg__
 657 032c 0FB6      		in __tmp_reg__,__SREG__
 658 032e 0F92      		push __tmp_reg__
 659 0330 1124      		clr __zero_reg__
 660 0332 2F93      		push r18
 661 0334 3F93      		push r19
 662 0336 4F93      		push r20
 663 0338 5F93      		push r21
 664 033a 6F93      		push r22
 665 033c 7F93      		push r23
 666 033e 8F93      		push r24
 667 0340 9F93      		push r25
 668 0342 AF93      		push r26
 669 0344 BF93      		push r27
 670 0346 EF93      		push r30
 671 0348 FF93      		push r31
 672               	/* prologue end (size=17) */
 673               	.LM89:
 674 034a 0E94 0000 		call SingleResponseIsr
 675               	/* epilogue: frame size=0 */
 676 034e FF91      		pop r31
 677 0350 EF91      		pop r30
 678 0352 BF91      		pop r27
 679 0354 AF91      		pop r26
 680 0356 9F91      		pop r25
 681 0358 8F91      		pop r24
 682 035a 7F91      		pop r23
 683 035c 6F91      		pop r22
 684 035e 5F91      		pop r21
 685 0360 4F91      		pop r20
 686 0362 3F91      		pop r19
 687 0364 2F91      		pop r18
 688 0366 0F90      		pop __tmp_reg__
 689 0368 0FBE      		out __SREG__,__tmp_reg__
 690 036a 0F90      		pop __tmp_reg__
 691 036c 1F90      		pop __zero_reg__
 692 036e 1895      		reti
 693               	/* epilogue end (size=17) */
 694               	/* function __vector_3 size 36 (2) */
 695               	.LFE15:
 697               	.global	init_Rfid
 699               	init_Rfid:
 700               	.LFB13:
 701               	.LM90:
 702               	/* prologue: frame size=0 */
 703               	/* prologue end (size=0) */
 704               	.LVL36:
 705               	.LM91:
 706 0370 0E94 0000 		call Mf500PcdConfig
 707               	.LVL37:
 708 0374 8823      		tst r24
 709 0376 01F0      		breq .L74
 710               	.LM92:
 711 0378 0E94 0000 		call Mf500PcdConfig
 712               	.L74: