rsic.smp_dump.txt

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

State Machine - |rsic|Control_Unit:M1_Controller|state
Name state.S_fet1 state.S_fet2 state.S_dec state.S_ex1 state.S_cmp state.S_rd1 state.S_wr1 state.S_lw state.S_rw state.S_br1 state.S_brz state.S_halt state.S_idle 
state.S_idle 0 0 0 0 0 0 0 0 0 0 0 0 0 
state.S_halt 0 0 0 0 0 0 0 0 0 0 0 1 1 
state.S_brz 0 0 0 0 0 0 0 0 0 0 1 0 1 
state.S_br1 0 0 0 0 0 0 0 0 0 1 0 0 1 
state.S_rw 0 0 0 0 0 0 0 0 1 0 0 0 1 
state.S_lw 0 0 0 0 0 0 0 1 0 0 0 0 1 
state.S_wr1 0 0 0 0 0 0 1 0 0 0 0 0 1 
state.S_rd1 0 0 0 0 0 1 0 0 0 0 0 0 1 
state.S_cmp 0 0 0 0 1 0 0 0 0 0 0 0 1 
state.S_ex1 0 0 0 1 0 0 0 0 0 0 0 0 1 
state.S_dec 0 0 1 0 0 0 0 0 0 0 0 0 1 
state.S_fet2 0 1 0 0 0 0 0 0 0 0 0 0 1 
state.S_fet1 1 0 0 0 0 0 0 0 0 0 0 0 1