rsic.map.qmsg

这是我同学在上海交大实习的时候做的一个单片机的verilog代码实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 29 10:34:12 2008 " "Info: Processing started: Tue Jul 29 10:34:12 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off rsic -c rsic " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rsic -c rsic" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/rsic/rsic.v " "Warning: Can't analyze file -- file E:/rsic/rsic.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RISC_SPM.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RISC_SPM.v" { { "Info" "ISGN_ENTITY_NAME" "1 rsic " "Info: Found entity 1: rsic" {  } { { "RISC_SPM.v" "" { Text "E:/rsic/RISC_SPM.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "Control_Unit.v(55) " "Warning (10273): Verilog HDL warning at Control_Unit.v(55): sign extended using \"x\" or \"z\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 55 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: sign extended using \"x\" or \"z\"" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "Control_Unit.v(59) " "Warning (10273): Verilog HDL warning at Control_Unit.v(59): sign extended using \"x\" or \"z\"" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 59 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: sign extended using \"x\" or \"z\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Control_Unit.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Control_Unit.v" { { "Info" "ISGN_ENTITY_NAME" "1 Control_Unit " "Info: Found entity 1: Control_Unit" {  } { { "Control_Unit.v" "" { Text "E:/rsic/Control_Unit.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Memory_Unit.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Memory_Unit.v" { { "Info" "ISGN_ENTITY_NAME" "1 Memory_Unit " "Info: Found entity 1: Memory_Unit" {  } { { "Memory_Unit.v" "" { Text "E:/rsic/Memory_Unit.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "Processing_Unit.v(134) " "Warning (10273): Verilog HDL warning at Processing_Unit.v(134): sign extended using \"x\" or \"z\"" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 134 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: sign extended using \"x\" or \"z\"" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "Processing_Unit.v(145) " "Warning (10273): Verilog HDL warning at Processing_Unit.v(145): sign extended using \"x\" or \"z\"" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 145 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: sign extended using \"x\" or \"z\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Processing_Unit.v 9 9 " "Info: Found 9 design units, including 9 entities, in source file Processing_Unit.v" { { "Info" "ISGN_ENTITY_NAME" "1 Processing_Unit " "Info: Found entity 1: Processing_Unit" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 Register_Unit " "Info: Found entity 2: Register_Unit" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 D_flop " "Info: Found entity 3: D_flop" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 59 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 Address_Register " "Info: Found entity 4: Address_Register" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 73 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 Instruction_Register " "Info: Found entity 5: Instruction_Register" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 87 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 Program_Counter " "Info: Found entity 6: Program_Counter" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 101 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 Multiplexer_6ch " "Info: Found entity 7: Multiplexer_6ch" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 123 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 Multiplexer_3ch " "Info: Found entity 8: Multiplexer_3ch" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 137 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 Alu_RISC " "Info: Found entity 9: Alu_RISC" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 158 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "rsic " "Info: Elaborating entity \"rsic\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Processing_Unit Processing_Unit:M0_Processor " "Info: Elaborating entity \"Processing_Unit\" for hierarchy \"Processing_Unit:M0_Processor\"" {  } { { "RISC_SPM.v" "M0_Processor" { Text "E:/rsic/RISC_SPM.v" 21 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Register_Unit Processing_Unit:M0_Processor\|Register_Unit:R0 " "Info: Elaborating entity \"Register_Unit\" for hierarchy \"Processing_Unit:M0_Processor\|Register_Unit:R0\"" {  } { { "Processing_Unit.v" "R0" { Text "E:/rsic/Processing_Unit.v" 29 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "D_flop Processing_Unit:M0_Processor\|D_flop:Reg_Z " "Info: Elaborating entity \"D_flop\" for hierarchy \"Processing_Unit:M0_Processor\|D_flop:Reg_Z\"" {  } { { "Processing_Unit.v" "Reg_Z" { Text "E:/rsic/Processing_Unit.v" 34 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Address_Register Processing_Unit:M0_Processor\|Address_Register:Add_R " "Info: Elaborating entity \"Address_Register\" for hierarchy \"Processing_Unit:M0_Processor\|Address_Register:Add_R\"" {  } { { "Processing_Unit.v" "Add_R" { Text "E:/rsic/Processing_Unit.v" 36 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Instruction_Register Processing_Unit:M0_Processor\|Instruction_Register:IR " "Info: Elaborating entity \"Instruction_Register\" for hierarchy \"Processing_Unit:M0_Processor\|Instruction_Register:IR\"" {  } { { "Processing_Unit.v" "IR" { Text "E:/rsic/Processing_Unit.v" 37 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Program_Counter Processing_Unit:M0_Processor\|Program_Counter:PC " "Info: Elaborating entity \"Program_Counter\" for hierarchy \"Processing_Unit:M0_Processor\|Program_Counter:PC\"" {  } { { "Processing_Unit.v" "PC" { Text "E:/rsic/Processing_Unit.v" 38 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 Processing_Unit.v(118) " "Warning (10230): Verilog HDL assignment warning at Processing_Unit.v(118): truncated value with size 32 to match size of target (8)" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Multiplexer_6ch Processing_Unit:M0_Processor\|Multiplexer_6ch:Mux_1 " "Info: Elaborating entity \"Multiplexer_6ch\" for hierarchy \"Processing_Unit:M0_Processor\|Multiplexer_6ch:Mux_1\"" {  } { { "Processing_Unit.v" "Mux_1" { Text "E:/rsic/Processing_Unit.v" 39 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 Processing_Unit.v(129) " "Warning (10230): Verilog HDL assignment warning at Processing_Unit.v(129): truncated value with size 32 to match size of target (16)" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 129 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Multiplexer_3ch Processing_Unit:M0_Processor\|Multiplexer_3ch:Mux_2 " "Info: Elaborating entity \"Multiplexer_3ch\" for hierarchy \"Processing_Unit:M0_Processor\|Multiplexer_3ch:Mux_2\"" {  } { { "Processing_Unit.v" "Mux_2" { Text "E:/rsic/Processing_Unit.v" 40 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 Processing_Unit.v(143) " "Warning (10230): Verilog HDL assignment warning at Processing_Unit.v(143): truncated value with size 32 to match size of target (16)" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 143 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Alu_RISC Processing_Unit:M0_Processor\|Alu_RISC:ALU " "Info: Elaborating entity \"Alu_RISC\" for hierarchy \"Processing_Unit:M0_Processor\|Alu_RISC:ALU\"" {  } { { "Processing_Unit.v" "ALU" { Text "E:/rsic/Processing_Unit.v" 41 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "RD Processing_Unit.v(167) " "Warning (10036): Verilog HDL or VHDL warning at Processing_Unit.v(167): object \"RD\" assigned a value but never read" {  } { { "Processing_Unit.v" "" { Text "E:/rsic/Processing_Unit.v" 167 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}