cpu.inc

TCP/IP stack, web application, CGI function

.if	RD2
;
; SPECIAL REGISTER
;
	.equ	AUXR,	0x8E
	.equ	CKCON,	0x8F
	.equ	AUXR1,  0xA2
	.equ	WDTRST, 0xA6
	.equ	WDTPRG, 0xA7
	.equ	EECON,  0xD2
	.equ	EETIM,  0xD3
	.equ	EEE,    0b00000010
	.equ	EEBUSY, 0b00000001
	.equ	EXTRAM, 0b00000010
;# Watchdog timing #
	.local	WATCHDOG
	.equ	WATCHDOG,0b00000111
	;2.09s @ 12 MHz

.macro	ENABLE_EE
	mov	EECON,#EEE		;enable EEPROM
.endm
.macro	DISABLE_EE
	mov	EECON,#0		;disable EEPROM
.endm
.macro	ENABLE_XRAM
	anl	AUXR,#(~EXTRAM)
.endm
.macro	DISABLE_XRAM
	orl	AUXR,#EXTRAM
.endm
.macro	ENABLE_DPTR2
	inc	AUXR1			;select DPTR'
.endm
.macro	DISABLE_DPTR2
	dec	AUXR1			;select DPTR
.endm

.macro	ENABLE_EE_DPTR2
	mov	EECON,#EEE		;enable EEPROM
	inc	AUXR1			;select DPTR'
.endm
.macro	DISABLE_EE_DPTR2
	mov	EECON,#0		;disable EEPROM
	dec	AUXR1			;select DPTR
.endm
.macro	INIT_WD
	mov	WDTPRG, #WATCHDOG
	mov	WDTRST,#0x1E		;restart Watchdog
	mov	WDTRST,#0xE1
.endm	
.macro	RESTART_WD
	mov	WDTRST,#0x1E		;restart Watchdog
	mov	WDTRST,#0xE1
.endm
	.equ	X2SETUP, 0b00001111	;AUXR settings
;			  ..0..... RD/, WR/ 6 clock length
;			  ..1..... RD/, WR/ 30 clock length
;			  ....11.. 1024 bytes XRAM
;			  ......1. External data memory access
;			  .......1 ALE only if MOVX or MOVC

	.equ	C2SETUP, 0b01000001
;			  .0...... WatchDog Clock 6 clock
;			  .1...... WatchDog Clock 12 clock
;			  ..0..... PCA Clock 6 clock
;			  ..1..... PCA Clock 12 clock
;			  ...0.... UART Clock 6 clock
;			  ...1.... UART Clock 12 clock
;			  ....0... Timer2 Clock 6 clock
;			  ....1... Timer2 Clock 12 clock
;			  .....0.. Timer1 Clock 6 clock
;			  .....1.. Timer1 Clock 12 clock
;			  ......0. Timer0 Clock 6 clock
;			  ......1. Timer0 Clock 12 clock
;			  .......0 CPU Clock 6 clock
;			  .......1 CPU Clock 12 clock
.else
;
; SPECIAL REGISTER
;
	.equ	DPH1,  0x85
	.equ	DPL1,  0x84
	.equ	WMCON, 0x96
	.equ	DPS,   0b00000100
	.equ	EEMEN, 0b00001000
	.equ	EEMWE, 0b00010000
;# Watchdog timing #
	.local	WATCHDOG, RESTARTWATCHDOG
	.equ	WATCHDOG,0b11100001	;2048 ms
	.equ	RESTARTWATCHDOG,0b11100011

.macro	ENABLE_EE
	orl	WMCON,#EEMEN		;enable EEPROM
.endm
.macro	DISABLE_EE
	anl	WMCON,#(~(EEMEN | EEMWE)) ;disable EEPROM
.endm
.macro	ENABLE_DPTR2
	orl	WMCON,#DPS		;select DPTR'
.endm
.macro	DISABLE_DPTR2
	anl	WMCON,#(~ DPS)		;select DPTR
.endm

.macro	ENABLE_EE_DPTR2
	orl	WMCON,#(EEMEN | DPS)	;enable EEPROM
 & select DPTR'
.endm
.macro	DISABLE_EE_DPTR2
	mov	WMCON,#WATCHDOG		;disable EEPROM & select DPTR
.endm
.macro	INIT_WD
.endm	
.macro	RESTART_WD
	mov	WMCON,#RESTARTWATCHDOG	;restart Watchdog
.endm
.endif

;
; SW EQU
;
	.local	RESENDMODE, NORESENDMODE
	.equ	RESENDMODE, 0xD2	;set bit
	.equ	NORESENDMODE, 0xC2	;reset bit
;
; TCP and Ethernet definition
;
	.equ	LASTSTACK1, 0x01
	.equ	LASTSTACK2, 0x02
;
; PCB EQU
;
	.equ	HW4, 0