8019.inc

TCP/IP stack, web application, CGI function

	.ifndef	PARAMINC
	.err missing include param.inc
	.endif

;a few useful Ethernet definitions.
	.equ	RUNT,60     		;smallest legal size packet, no fcs
	.equ	GIANT,1514            	;largest legal size packet, no fcs
	.equ	ETHER_ADDR_LEN,6        ;Ethernet address length.
;
	.equ	IP_ADDR_LEN,4
	.equ	IP_MAGIC1,0x4062	;'@b'
	.equ	IP_MAGIC2,0x636C	;'cl'
	.equ	IP_MAGIC,0x4062636C	;'@bcl'
;
.ifdef DUALSTACK
	.equ	TX_PAGES,1+6+6
.else
	.equ	TX_PAGES,1+6
.endif
	.equ	NE_START_PG,0x40        ;;First page of TX buffer
	.equ	NE_STOP_PG,0x60         ;;Last page + 1 of RX Ring
	.equ	RX_START_PG,NE_START_PG + TX_PAGES
	.equ	RX_CURR_PG,RX_START_PG + 1
	.equ	I2CBUS,0b01100000       ;;I2C data & clock

	.equ	stack0offset,	NE_START_PG	; 1 page
	.equ	stack1offset,	NE_START_PG+1	; 6 pages
	.equ	stack2offset,	NE_START_PG+1+6	; 6 pages

;;***************************************************************************
;/* Some generic ethernet register configurations. */
;#define E8390_TX_IRQ_MASK 0x0A /* For register EN0_ISR */
;#define E8390_RX_IRQ_MASK  0x05
;#define E8390_RXCONFIG 0x04    /* EN0_RXCR: broadcasts, no multicast,errors */
;#define E8390_RXOFF 0x20       /* EN0_RXCR: Accept no packets */
;#define E8390_TXCONFIG 0x00    /* EN0_TXCR: Normal transmit mode */
;#define E8390_TXOFF 0x02       /* EN0_TXCR: Transmitter off */

;;***************************************************************************
; The EN registers - the Realtek RTL8019AS chip registers
; There are four pages of registers in the chip. You select
; which page you want, then address them at offsets 00-0F from base.
; The chip command register (EN_CMD) appears in all pages.

	.equ	   EN_CMD,0       	;The command register (for all pages)
	.equ	   EN_DATA,0x10     	;Remote DMA Port (for all pages)
	.equ	   EN_RESET,0x1F     	;Reset Port (for all pages)

;;Register accessed at EN_CMD, the RTL8019 base addr
	.equ	   EN_STOP,0x01     	;Stop and reset the chip
	.equ	   EN_START,0x02     	;Start the chip, clear reset
	.equ	   EN_TRANS,0x04     	;Transmit a frame
	.equ	   BIT_TRANS,Acc.2   	;Transmit a frame
	.equ	   EN_RREAD,0x08	;Remote read
	.equ	   EN_RWRITE,0x10     	;Remote write
	.equ	   EN_NODMA,0x20     	;Remote DMA
	.equ	   EN_PAGE0,0x00     	;Select page chip registers
	.equ	   EN_PAGE1,0x40     	;using the two high-order bits
	.equ	   EN_PAGE2,0x80
	.equ	   EN_PAGE3,0xC0

;;Page 0 register offsets
	.equ	   EN0_CLDALO,0x01     	;RD Low byte of current local dma addr
	.equ	   EN0_STARTPG,0x01    	;WR Starting page of ring buffer
	.equ	   EN0_CLDAHI,0x02     	;RD High byte of current local dma addr
	.equ	   EN0_STOPPG,0x02     	;WR Ending page +1 of ring buffer
	.equ	   EN0_BOUNDARY,0x03   	;RD/WR Boundary page of ring buffer
	.equ	   EN0_TSR,0x04     	;RD Transmit status reg
	.equ	   EN0_TPSR,0x04     	;WR Transmit starting page
	.equ	   EN0_NCR,0x05     	;RD Number of collision reg
	.equ	   EN0_TCNTLO,0x05     	;WR Low  byte of tx byte count
	.equ	   EN0_FIFO,0x06     	;RD FIFO
	.equ	   EN0_TCNTHI,0x06     	;WR High byte of tx byte count
	.equ	   EN0_ISR,0x07     	;RD/WR Interrupt status reg
	.equ	   EN0_CRDALO,0x08     	;RD low byte of current remote dma address
	.equ	   EN0_RSARLO,0x08    	;WR Remote start address reg 0
	.equ	   EN0_CRDAHI,0x09     	;RD high byte, current remote dma address
	.equ	   EN0_RSARHI,0x09     	;WR Remote start address reg 1
	.equ	   EN0_RCNTLO,0x0a     	;WR Remote byte count reg
	.equ	   EN0_RCNTHI,0x0b     	;WR Remote byte count reg
	.equ	   EN0_RSR,0x0c     	;RD RX status reg
	.equ	   EN0_RXCR,0x0c     	;WR RX configuration reg
	.equ	   EN0_TXCR,0x0d     	;WR TX configuration reg
	.equ	   EN0_COUNTER0,0x0d	;RD Rcv alignment error counter
	.equ	   EN0_DCFG,0x0e     	;WR Data configuration reg
	.equ	   EN0_COUNTER1,0x0e   	;RD Rcv CRC error counter
	.equ	   EN0_IMR,0x0f     	;WR Interrupt mask reg
	.equ	   EN0_COUNTER2,0x0f   	;RD Rcv missed frame error counter

;; Bank0/Reg04
;;Bits in EN0_TSR - Transmitted packet status
	.equ	   ENTSR_PTX,0x01    	;Packet transmitted without error
	.equ	   ENTSR_ND,0x02     	;The transmit wasn't deferred.
	.equ	   ENTSR_COL,0x04     	;The transmit collided at least once.
	.equ	   ENTSR_ABT,0x08     	;The transmit collided 16 times, and was deferred.
	.equ	   ENTSR_CRS,0x10     	;The carrier sense was lost.
	.equ	   ENTSR_FU,0x20     	;A "FIFO underrun" occurred during transmit.
	.equ	   ENTSR_CDH,0x40     	;The collision detect "heartbeat" signal was lost.
	.equ	   ENTSR_OWC,0x80     	;There was an out-of-window collision.

;; Bank0/Reg07
;;Bits in EN0_ISR - Interrupt status register
	.equ	   ENISR_RX,0x01     	;Receiver, no error
	.equ	   BITISR_RX,Acc.0   	;Receiver, no error
	.equ	   ENISR_TX,0x02     	;Transmitter, no error
	.equ	   ENISR_RX_ERR,0x04   	;Receiver, with error
	.equ	   BITISR_RX_ERR,Acc.2	;Receiver, with error
	.equ	   ENISR_TX_ERR,0x08  	;Transmitter, with error
	.equ	   BITISR_TX_ERR,Acc.3	;Transmitter, with error
	.equ	   ENISR_OVER,0x10   	;Receiver overwrote the ring
	.equ	   BITISR_OVER,Acc.4 	;Receiver overwrote the ring
	.equ	   ENISR_COUNTERS,0x20	;Counters need emptying
	.equ	   BITISR_COUNTERS,Acc.5 ;Counters need emptying
	.equ	   ENISR_RDC,0x40	;remote dma complete
	.equ	   ENISR_RESET,0x80	;Reset completed
	.equ	   BITISR_RESET,Acc.7	;Reset completed
	.equ	   ENISR_ALL,0x3f	;Interrupts we will enable

;; Bank0/Reg0C
;;Bits in EN0_RSR and received packet status byte
	.equ	   ENRSR_RXOK,0x01	;Received a good packet
	.equ	   BITRSR_RXOK,Acc.0	;Received a good packet
	.equ	   ENRSR_CRC,0x02	;CRC error
	.equ	   ENRSR_FAE,0x04	;frame alignment error
	.equ	   ENRSR_FO,0x08	;FIFO overrun
	.equ	   ENRSR_MPA,0x10	;missed pkt
	.equ	   ENRSR_PHY,0x20	;physical/multicase address
	.equ	   ENRSR_DIS,0x40	;receiver disable. set in monitor mode
	.equ	   ENRSR_DEF,0x80	;deferring

;; Bank0/Reg0C
;;Bits in EN0_RXCR - RX configuration reg
	.equ	   ENRXCR_CRC,0x01	;Save error pkts
	.equ	   ENRXCR_RUNT,0x02	;Accept runt pkt
	.equ	   ENRXCR_BCST,0x04	;Accept broadcasts
	.equ	   ENRXCR_MULTI,0x08	;Multicast (if pass filter)
	.equ	   ENRXCR_PROMP,0x10	;Promiscuous physical addresses
	.equ	   ENRXCR_MON,0x20	;Monitor mode (no packets rcvd)

;; Bank0/Reg0D
;;Bits in EN0_TXCR - TX configuration reg
	.equ	   ENTXCR_CRC,0x01	;inhibit CRC, do not append crc
	.equ	   ENTXCR_LOOP,0x02	;set internal loopback mode
	.equ	   ENTXCR_LB01,0x06	;encoded loopback control
	.equ	   ENTXCR_ATD,0x08	;auto tx disable
	.equ	   ENTXCR_OFST,0x10	;collision offset enable

;; Bank0/Reg0E
;;Bits in EN0_DCFG - Data config register
#if WORDMODE
	.equ	   ENDCFG_WTS,0x01	;word transfer mode selection
#else
	.equ	   ENDCFG_WTS,0x00	;byte transfer mode selection
#endif
	.equ	   ENDCFG_BOS,0x02	;byte order selection
					;0: MD15-8, LSB on MD7-0
					;1: MSB on MD7-0, LSB on MD15-8
	.equ	   ENDCFG_LAS,0x04	;long addr selection (must be set to zero)
	.equ	   ENDCFG_BMS,0x08	;loopback select
					;0: Loopback mode select. Bits 1 and 2 of the
					;EN0_TXCR must also be programmed for Loopback
					;1: Normal operation
	.equ	   ENDCFG_ARM,0x10	;autoinitialize remote
	.equ	   ENDCFG_FT00,0x00	;fifo treshold
	.equ	   ENDCFG_FT01,0x20
	.equ	   ENDCFG_FT10,0x40
	.equ	   ENDCFG_FT11,0x60

;;Page 1 register offsets
	.equ	   EN1_PHYS,0x01	;RD/WR This board's physical enet addr
	.equ	   EN1_CURPAG,0x07	;RD/WR Current memory page
	.equ	   EN1_MULT,0x08	;RD/WR Multicast filter mask array (8 bytes)

;;Page 3 register offsets
	.equ	   EN3_9346CR,0x01	;9346 command register
	.equ	   EN1_CONFIG3,0x06	;RTL8019AS configuration register 3

;;***************************************************************************
;;Description of header of each packet in receive area of memory
;The 8019 specific per-packet-header format.
;struct e8019_pkt_hdr {
;  unsigned char status; /* status */
;  unsigned char next;   /* pointer to next packet. */
;  unsigned short count; /* header + packet length in bytes */
;}
	.equ	   EN_RBUF_STAT,0       ;Received frame status
	.equ	   EN_RBUF_NXT_PG,1     ;Page after this frame
	.equ	   EN_RBUF_SIZE_LO,2   	;Length of this frame
	.equ	   EN_RBUF_SIZE_HI,3    ;Length of this frame
	.equ	   SIZE_OF_8019_HDR,4   ;size of 8019 specific packet header

;;***************************************************************************
;struct {
;  WORD pktDest0, pktDest1, pktDest2;
;  WORD pktSrc0, pktSrc1, pktSrc2;
;  WORD pktType;
;} eth_pkt_hdr;
	.equ	   PKT_DEST,0
	.equ	   PKT_SRC,6
	.equ	   PKT_TYPE,12
	.equ	   SIZE_OF_ETH_PKT_HDR,14
;
; ARP
;
	.equ	   _ARP,SIZE_OF_ETH_PKT_HDR
	.equ	   ARP_HWTYPE,_ARP      ;14 hardware type (0001h)
	.equ	   ARP_PRTYPE,_ARP+2    ;16 protocol type (0800h)
	.equ	   ARP_HWLEN,_ARP+4     ;18 hardware address length (06h)
	.equ	   ARP_PRLEN,_ARP+5     ;19 protocol address length (04h)
	.equ	   ARP_OP,_ARP+6        ;20 ARP operation (1=request, 2=reply)
	.equ	   ARP_SHWA,_ARP+8      ;22 senders hardware address
	.equ	   ARP_SIPA,_ARP+14     ;28 senders IP address
	.equ	   ARP_THWA,_ARP+18     ;32 target hardware address
	.equ	   ARP_TIPA,_ARP+24     ;38 target IP address
	.equ	   SIZE_OF_ARP,28       ;42
;
; IP header
;
	.equ	   _IP,SIZE_OF_ETH_PKT_HDR
	.equ	   IP_VERLEN,_IP        ;14 IP version(:4) and header length(:4)(in longs)
	.equ	   IP_TOS,_IP+1         ;15 IP type of service
	.equ	   IP_LEN,_IP+2         ;16 packet length (length-header_length)
	.equ	   IP_ID,_IP+4          ;18 datagram id
	.equ	   IP_FRAGOFF,_IP+6     ;20 fragment offset (frags:3,fo:13)
	.equ	   IP_TTL,_IP+8         ;22 time to live (in gateway hops)
	.equ	   IP_PROTO,_IP+9       ;23 protocol (ICMP=1, TCP=6, EGP=8, UDP=17)
	.equ	   IP_CKSUM,_IP+10      ;24 header checksum
	.equ	   IP_SRCADDR,_IP+12    ;26 IP address of source
	.equ	   IP_DSTADDR,_IP+16    ;30 IP addess of destination
	.equ	   IP_DATA,_IP+20       ;34
	.equ	   IP_HEADER_LEN,20
;
; ARP value equates
;
	.equ	   ARPT_RQ,1       	;ARP request
	.equ	   ARPT_REPLY,2       	;ARP reply
;
; IP value equates
;
	.equ	   IPT_ICMP,1           ;protocol type for ICMP packets
	.equ	   IPT_TCP,6            ;protocol type for TCP packets
	.equ	   IPT_EGP,8            ;protocol type for EGP packets
	.equ	   IPT_UDP,0x11         ;protocol type for UDP packets
;
; ICMP header
;
	.equ	   IC_TYPE,IP_DATA      ;0=reply, 8=request, others=who-cares
	.equ	   IC_CODE,IC_TYPE+1    ;code
	.equ	   IC_CKSUM,IC_CODE+1   ;checksum of header+data
	.equ	   IC_ID,IC_CKSUM+2     ;message id
	.equ	   IC_SEQ,IC_ID+2       ;sequence number
;
; UDP Header
;
	.equ	   UDP_SRC,IP_DATA      ;34 source udp port number
	.equ	   UDP_DST,UDP_SRC+2    ;36 destination UDP port number
	.equ	   UDP_LEN,UDP_DST+2    ;38 length of UDP header+data
	.equ	   UDP_CKSUM,UDP_LEN+2  ;40 checksum  (see note)
	.equ	   UDP_DATA,UDP_CKSUM+2 ;42 start of data
	.equ	   UDP_HEADER_LEN,8
;
; Note: checksum is calculated by taking the 16 bit sums of the ip_src, ip_dst,
; ip_proto, u_len, and the sum starting at u_src for a length of u_len
; yes, this means that u_len is taken twice! u_cksum is zero during the calc.
; The sum is then one's complemented. This is the checksum
;
; TCP Header
;
;    word            dstPort;
;    longword        seqnum;
;    longword        acknum;
;    word            flags;
;    word            window;
;    word            checksum;
;    word            urgentPointer;
	.equ	   _TCP,SIZE_OF_ETH_PKT_HDR + IP_HEADER_LEN
	.equ	   TCP_HEADER,_TCP+0
	.equ	   TCP_SP,_TCP+0  	;word   srcPort
	.equ	   TCP_DP,_TCP+2  	;word   dstPort
	.equ	   TCP_SEQ,_TCP+4  	;longword seqnum
	.equ	   TCP_ACK,_TCP+8  	;longword acknum
	.equ	   TCP_FLAGS,_TCP+12 	;word   flags
	.equ	   TCP_WIN,_TCP+14 	;word   window
	.equ	   TCP_CHKSUM,_TCP+16 	;word   checksum
	.equ	   TCP_URG,_TCP+18 	;word   urgentPointer
	.equ	   TCP_DATA,_TCP+20
       	.equ	   TCP_HEADER_LEN,20
;
; WWW8051 TCP parameters
;
	.equ	mss80, 1460	;40 byte header + ... byte data
;	.equ	win80, 0x0C00	;0x2000	;... byte data
	.equ	win80, 1460	;... byte data
;
; WWW8051 TCP state machine flags
;
	.equ	stateArpSent, 0
	.equ	stateSynSent, 1
	.equ	stateEstablished, 2
	.equ	stateSyn, 3