cpuinit.s

LPC2220的Bootloader自己写的,和 周立功的模版实现完全不一样

;//***************************************************************
;//  ARM BOOT ROUTE VER1.0 for NXP_ARM release
;//  [e-mail]
;//  chenjun @ 2008-7-19
;//***************************************************************

	
	INCLUDE	NXP_ARM.s
	INCLUDE	LPC2220RM_DEMO_DSP.s

	CODE32
	AREA    InitSystemBlk,	CODE,	READONLY

	EXPORT	InitCPU
InitCPU
	;//set pinsel2
	ldr r0, =rPINSEL2
	ldr r1,	=0x0f014914
	str	r1, [r0]
	
	;//set memory controller			
	adr	r0, InitCPU
	ldr	r1, =InitCPU
	sub	r0, r1, r0		
	ldr	r1, =SMRDATA
	sub	r0, r1, r0 
	ldmia   r0, {r1-r4}
	ldr	    r0, =rBCFG0
	stmia   r0, {r1-r4}	

	;//initial stack
	mrs	r0, cpsr
	bic	r0, r0, #ModeMask
	
	orr	r1, r0, #UDF|I
	msr	cpsr_cxsf, r1		;//UndefMode
	ldr	sp,=UndefStack
	
	orr	r1, r0, #ABT|I
	msr	cpsr_cxsf, r1		;//AbortMode
	ldr	sp, =AbortStack
	
	orr	r1, r0, #IRQ|I
	msr	cpsr_cxsf, r1		;//IRQMode
	ldr	sp, =IRQStack
	
	orr	r1, r0, #FIQ|I
	msr	cpsr_cxsf, r1		;//FIQMode
	ldr	sp, =FIQStack	
		
	orr	r1, r0, #SVC|I
	msr	cpsr_cxsf, r1		;//SVCMode
	ldr	sp, =SVCStack

	ldr	r0, =IRQ_SVC_VECTOR	
	ldr	r1, =IRQ_SERVICE			
	str	r1, [r0]			

	ldr	r0, =FIQ_SVC_VECTOR	
	ldr	r1, =FIQ_SERVICE			
	str	r1, [r0]	

	mov	pc, lr				

;//************************************************************************************************************************************************************************************************************************
SMRDATA DATA
    
	DCD 	((B0_MW<<28)+(B0_BM<<27)+(B0_WP<<26)+(B0_WST2<<11)+(B0_RBLE<<10)+(B0_WST1<<5)+B0_IDCY);//BCFG0
	DCD 	((B1_MW<<28)+(B1_BM<<27)+(B1_WP<<26)+(B1_WST2<<11)+(B1_RBLE<<10)+(B1_WST1<<5)+B1_IDCY);//BCFG1 
	DCD 	((B2_MW<<28)+(B2_BM<<27)+(B2_WP<<26)+(B2_WST2<<11)+(B2_RBLE<<10)+(B2_WST1<<5)+B2_IDCY);//BCFG2
	DCD 	((B3_MW<<28)+(B3_BM<<27)+(B3_WP<<26)+(B3_WST2<<11)+(B3_RBLE<<10)+(B3_WST1<<5)+B3_IDCY);//BCFG3

	ALIGN	

;//************************************************************************************************************************************************************************************************************************
IRQ_SERVICE				;//using rI_ISPR register.		   	
    sub	    sp,sp,#4	;//reserved for PC
    stmfd   sp!,{r8-r9}   

	;//IMPORTANT CAUTION
	;//if rI_ISPC is not used properly, rI_ISPR can be 0 in this routine.

    ldr	    r9,=rVICIRQStatus
    ldr	    r9,[r9]
	cmp		r9, #0x0	;//If the IDLE mode work-around is used,
						;//r9 may be 0 sometimes.
	beq		%F2
    mov	    r8,#0x0
0
    movs    r9,r9,lsr #1
    bcs	    %F1
    add	    r8,r8,#4
    b	    %B0
1
    ldr	    r9,=HandleADC
    add	    r9,r9,r8
    ldr	    r9,[r9]
    str	    r9,[sp,#8]
    ldmfd   sp!,{r8-r9,pc}
2
	ldmfd	sp!,{r8-r9}
	add		sp,sp,#4
	subs	pc,lr,#4
	
;//************************************************************************************************************************************************************************************************************************
FIQ_SERVICE				;//using rF_ISPR register.		   	
    sub	    sp,sp,#4	;//reserved for PC
    stmfd   sp!,{r8-r9}   

	;//IMPORTANT CAUTION
	;//if rF_ISPR is not used properly, rF_ISPR can be 0 in this routine.

    ldr	    r9,=rVICFIQStatus
    ldr	    r9,[r9]
	cmp		r9, #0x0	;If the IDLE mode work-around is used,
						;r9 may be 0 sometimes.
	beq		%F2
    mov	    r8,#0x0
0
    movs    r9,r9,lsr #1
    bcs	    %F1
    add	    r8,r8,#4
    b	    %B0
1
    ldr	    r9,=HandleADC
    add	    r9,r9,r8
    ldr	    r9,[r9]
    str	    r9,[sp,#8]
    ldmfd   sp!,{r8-r9,pc}
2
	ldmfd	sp!,{r8-r9}
	add		sp,sp,#4
	subs	pc,lr,#4

;//************************************************************************************************************************************************************************************************************************
	AREA RamData, DATA, READWRITE	

	^	(StackBase + 0x3000)
SVCStack	#	0x800	;//0x4000_a000 - 0x4000_cfff     0x3000
UndefStack	#	0x800	;//0x4000_d000 - 0x4000_d7ff     0x800
AbortStack	#	0x1000	;//0x4000_d800 - 0x4000_dfff     0x800
IRQStack	#	0x1000	;//0x4000_e000 - 0x4000_efff     0x1000
FIQStack	#	0x0		;//0x4000_f000 - 0x4000_ffff     0x1000

	^	(StackBase - 0x6c)
SYS_RST_VECTOR	#	4	
UDF_INS_VECTOR	#	4	
SWI_SVC_VECTOR	#	4
INS_ABT_VECTOR	#	4
DAT_ABT_VECTOR	#	4
RESERVED_VECTOR	#	4
IRQ_SVC_VECTOR	#	4
FIQ_SVC_VECTOR	#	4

HandleADC		#	4
HandleEINT3		#	4
HandleEINT2		#	4
HandleEINT1		#	4
HandleEINT0		#	4
HandleRTC		#	4
HandlePLL		#	4
HandleSPI1_SSP	#	4
HandleSPI0		#	4
HandleI2C		#	4
HandlePWM		#	4
HandleUART1		#	4
HandleUART0		#	4
HandleTIMER1	#	4
HandleTIMER0	#	4
HandleARMCore1	#	4
HandleARMCore2	#	4
HandleSoftInt	#	4
HandleWDT		#	4

	EXPORT	StackBase
	EXPORT	UDF_INS_VECTOR
	EXPORT	SWI_SVC_VECTOR
	EXPORT	INS_ABT_VECTOR
	EXPORT	DAT_ABT_VECTOR
	EXPORT	IRQ_SVC_VECTOR
	EXPORT	FIQ_SVC_VECTOR

	END