traffic.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Cell Usage :
# BELS                             : 124
#      GND                         : 1
#      INV                         : 7
#      LUT1                        : 24
#      LUT2                        : 3
#      LUT2_L                      : 1
#      LUT3                        : 1
#      LUT3_L                      : 3
#      LUT4                        : 14
#      LUT4_D                      : 4
#      LUT4_L                      : 13
#      MUXCY                       : 24
#      MUXF5                       : 3
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 24
# FlipFlops/Latches                : 38
#      FDC                         : 34
#      FDP                         : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 29
#      IBUF                        : 1
#      OBUF                        : 28
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                      34  out of    768     4%  
 Number of Slice Flip Flops:            38  out of   1536     2%  
 Number of 4 input LUTs:                63  out of   1536     4%  
 Number of bonded IOBs:                 30  out of     96    31%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 25    |
div_cnt_24:Q                       | NONE                   | 11    |
div_cnt_15:Q                       | NONE                   | 2     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 8.972ns (Maximum Frequency: 111.458MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 11.486ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.423ns (frequency: 184.400MHz)
  Total number of paths / destination ports: 325 / 25
-------------------------------------------------------------------------
Delay:               5.423ns (Levels of Logic = 26)
  Source:            div_cnt_0 (FF)
  Destination:       div_cnt_24 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: div_cnt_0 to div_cnt_24
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              1   1.085   1.035  div_cnt_0 (div_cnt_0)
     INV:I->O              2   0.549   0.000  traffic_div_cnt__n0000<0>lut_INV_0 (N5)
     MUXCY:S->O            1   0.659   0.000  traffic_div_cnt__n0000<0>cy (traffic_div_cnt__n0000<0>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<1>cy (traffic_div_cnt__n0000<1>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<2>cy (traffic_div_cnt__n0000<2>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<3>cy (traffic_div_cnt__n0000<3>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<4>cy (traffic_div_cnt__n0000<4>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<5>cy (traffic_div_cnt__n0000<5>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<6>cy (traffic_div_cnt__n0000<6>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<7>cy (traffic_div_cnt__n0000<7>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<8>cy (traffic_div_cnt__n0000<8>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<9>cy (traffic_div_cnt__n0000<9>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<10>cy (traffic_div_cnt__n0000<10>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<11>cy (traffic_div_cnt__n0000<11>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<12>cy (traffic_div_cnt__n0000<12>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<13>cy (traffic_div_cnt__n0000<13>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<14>cy (traffic_div_cnt__n0000<14>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<15>cy (traffic_div_cnt__n0000<15>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<16>cy (traffic_div_cnt__n0000<16>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<17>cy (traffic_div_cnt__n0000<17>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<18>cy (traffic_div_cnt__n0000<18>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<19>cy (traffic_div_cnt__n0000<19>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<20>cy (traffic_div_cnt__n0000<20>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<21>cy (traffic_div_cnt__n0000<21>_cyo)
     MUXCY:CI->O           1   0.042   0.000  traffic_div_cnt__n0000<22>cy (traffic_div_cnt__n0000<22>_cyo)
     MUXCY:CI->O           0   0.042   0.000  traffic_div_cnt__n0000<23>cy (traffic_div_cnt__n0000<23>_cyo)
     XORCY:CI->O           1   0.420   0.000  traffic_div_cnt__n0000<24>_xor (div_cnt__n0000<24>)
     FDC:D                     0.709          div_cnt_24
    ----------------------------------------
    Total                      5.423ns (4.388ns logic, 1.035ns route)
                                       (80.9% logic, 19.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'div_cnt_24:Q'
  Clock period: 8.972ns (frequency: 111.458MHz)
  Total number of paths / destination ports: 266 / 11
-------------------------------------------------------------------------
Delay:               8.972ns (Levels of Logic = 4)
  Source:            second_1 (FF)
  Destination:       second_1 (FF)
  Source Clock:      div_cnt_24:Q rising
  Destination Clock: div_cnt_24:Q rising

  Data Path: second_1 to second_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              6   1.085   1.665  second_1 (second_1)
     LUT4_D:I2->O         11   0.549   2.070  _n00171 (_n0017)
     LUT2_L:I1->LO         1   0.549   0.000  Ker1_F (N80)
     MUXF5:I0->O           2   0.315   1.206  Ker1 (N11)
     MUXF5:S->O            1   0.824   0.000  _n0013<1> (_n0013<1>)
     FDP:D                     0.709          second_1
    ----------------------------------------
    Total                      8.972ns (4.031ns logic, 4.941ns route)
                                       (44.9% logic, 55.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'div_cnt_15:Q'
  Clock period: 5.043ns (frequency: 198.295MHz)
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               5.043ns (Levels of Logic = 1)
  Source:            en_xhdl_1 (FF)
  Destination:       en_xhdl_1 (FF)
  Source Clock:      div_cnt_15:Q rising
  Destination Clock: div_cnt_15:Q rising

  Data Path: en_xhdl_1 to en_xhdl_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              6   1.085   1.665  en_xhdl_1 (en_xhdl_1)
     INV:I->O              1   0.549   1.035  _n00391_INV_0 (_n0039)
     FDP:D                     0.709          en_xhdl_1
    ----------------------------------------
    Total                      5.043ns (2.343ns logic, 2.700ns route)
                                       (46.5% logic, 53.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'div_cnt_15:Q'
  Total number of paths / destination ports: 58 / 9
-------------------------------------------------------------------------
Offset:              11.306ns (Levels of Logic = 3)
  Source:            en_xhdl_0 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      div_cnt_15:Q rising

  Data Path: en_xhdl_0 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              6   1.085   1.665  en_xhdl_0 (en_xhdl_0)
     LUT4:I0->O            7   0.549   1.755  data4<0>1 (data4<0>)
     LUT4:I0->O            1   0.549   1.035  Mrom_dataout_xhdl1_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 4.668          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                     11.306ns (6.851ns logic, 4.455ns route)
                                       (60.6% logic, 39.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'div_cnt_24:Q'
  Total number of paths / destination ports: 68 / 19
-------------------------------------------------------------------------
Offset:              11.486ns (Levels of Logic = 3)
  Source:            first_0 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      div_cnt_24:Q rising

  Data Path: first_0 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              8   1.085   1.845  first_0 (first_0)
     LUT4:I2->O            7   0.549   1.755  data4<0>1 (data4<0>)
     LUT4:I0->O            1   0.549   1.035  Mrom_dataout_xhdl1_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 4.668          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                     11.486ns (6.851ns logic, 4.635ns route)
                                       (59.6% logic, 40.4% route)

=========================================================================
CPU : 7.70 / 8.12 s | Elapsed : 8.00 / 8.00 s
 
--> 

Total memory usage is 76804 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    3 (   0 filtered)