traffic.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.37 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.37 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: traffic.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "traffic.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "traffic"
Output Format                      : NGC
Target Device                      : xc2s50-6-TQ144

---- Source Options
Top Module Name                    : traffic
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : traffic.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/TRAFFIC is now defined in a different file: was E:/temp/95144/vhdl/traffic/traffic.vhd, now is E:/temp/SPARTAN2/vhdl/complex/traffic/traffic.vhd
WARNING:HDLParsers:3215 - Unit work/TRAFFIC/ARCH is now defined in a different file: was E:/temp/95144/vhdl/traffic/traffic.vhd, now is E:/temp/SPARTAN2/vhdl/complex/traffic/traffic.vhd
Compiling vhdl file "E:/temp/SPARTAN2/vhdl/complex/traffic/traffic.vhd" in Library work.
Architecture arch of Entity traffic is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <traffic> (Architecture <arch>).
WARNING:Xst:819 - "E:/temp/SPARTAN2/vhdl/complex/traffic/traffic.vhd" line 58: The following signals are missing in the process sensitivity list:
   div_cnt<24>.
INFO:Xst:1561 - "E:/temp/SPARTAN2/vhdl/complex/traffic/traffic.vhd" line 181: Mux is complete : default of case is discarded
Entity <traffic> analyzed. Unit <traffic> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <traffic>.
    Related source file is "E:/temp/SPARTAN2/vhdl/complex/traffic/traffic.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 2                                              |
    | Outputs            | 15                                             |
    | Clock              | div_cnt<24> (rising_edge)                      |
    | Reset              | rst (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x8-bit ROM for signal <dataout_xhdl1>.
    Found 4-bit subtractor for signal <$n0014> created at line 60.
    Found 4-bit subtractor for signal <$n0015> created at line 60.
    Found 25-bit up counter for signal <div_cnt>.
    Found 2-bit register for signal <en_xhdl>.
    Found 4-bit register for signal <first>.
    Found 4-bit register for signal <second>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred   6 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <traffic> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:3]> with speed1 encoding.
-------------------
 State | Encoding
-------------------
 00    | 100
 01    | 001
 10    | 010
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 2
 4-bit subtractor                  : 2
# Counters                         : 1
 25-bit up counter                 : 1
# Registers                        : 7
 1-bit register                    : 5
 4-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <traffic> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block traffic, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : traffic.ngr
Top Level Output File Name         : traffic
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 30

Macro Statistics :
# ROMs                             : 1
#      16x8-bit ROM                : 1
# Registers                        : 8
#      1-bit register              : 6
#      25-bit register             : 1
#      4-bit register              : 1
# Adders/Subtractors               : 3
#      25-bit adder                : 1
#      4-bit subtractor            : 2