📄 traffic.rpt
字号:
FDCPE_first1: FDCPE port map (first(1),first_D(1),div_cnt(24),NOT rst,'0');
first_D(1) <= ((div_cnt(8).EXP)
OR (div_cnt(9).EXP)
OR (first(0) AND NOT first(1))
OR (NOT first(0) AND first(1))
OR (second(0) AND lightG(3) AND NOT lightY(3)));
FTCPE_first2: FTCPE port map (first(2),first_T(2),div_cnt(24),NOT rst,'0');
first_T(2) <= ((dataout_1_OBUF.EXP)
OR (EXP13_.EXP)
OR (NOT first(0) AND NOT first(1) AND first(3) AND NOT lightG(3))
OR (NOT first(0) AND NOT first(1) AND first(3) AND lightY(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT second(1) AND
NOT second(2) AND first(3) AND NOT second(3)));
FDCPE_first3: FDCPE port map (first(3),first_D(3),div_cnt(24),NOT rst,'0');
first_D(3) <= ((en_xhdl(0).EXP)
OR (first(0) AND NOT first(3) AND lightY(3))
OR (first(1) AND NOT first(3) AND lightY(3))
OR (first(2) AND NOT first(3) AND lightY(3)));
FDCPE_lightG0: FDCPE port map (lightG(0),lightG_D(0),div_cnt(24),'0',NOT rst);
lightG_D(0) <= lightG(3)
XOR
lightG_D(0) <= ((NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND NOT lightG(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND lightY(3)));
FDCPE_lightG1: FDCPE port map (lightG(1),lightG_D(1),div_cnt(24),'0',NOT rst);
lightG_D(1) <= lightG(3)
XOR
lightG_D(1) <= ((NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND NOT lightG(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND lightY(3)));
FDCPE_lightG2: FDCPE port map (lightG(2),lightG_D(2),div_cnt(24),'0',NOT rst);
lightG_D(2) <= lightG(3)
XOR
lightG_D(2) <= ((NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND NOT lightG(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND lightY(3)));
FTCPE_lightG3: FTCPE port map (lightG(3),lightG_T(3),div_cnt(24),'0',NOT rst);
lightG_T(3) <= ((NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND NOT lightG(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND lightY(3)));
lightR(0) <= NOT ((lightG(3) AND lightY(3)));
lightR(1) <= NOT ((lightG(3) AND lightY(3)));
lightR(2) <= NOT ((lightG(3) AND lightY(3)));
lightR(3) <= NOT ((lightG(3) AND lightY(3)));
FDCPE_lightY0: FDCPE port map (lightY(0),lightY_D(0),div_cnt(24),'0',NOT rst);
lightY_D(0) <= lightY(3)
XOR
lightY_D(0) <= ((NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND lightG(3) AND
NOT lightY(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND NOT lightG(3) AND
lightY(3)));
FDCPE_lightY1: FDCPE port map (lightY(1),lightY_D(1),div_cnt(24),'0',NOT rst);
lightY_D(1) <= lightY(3)
XOR
lightY_D(1) <= ((NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND lightG(3) AND
NOT lightY(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND NOT lightG(3) AND
lightY(3)));
FDCPE_lightY2: FDCPE port map (lightY(2),lightY_D(2),div_cnt(24),'0',NOT rst);
lightY_D(2) <= lightY(3)
XOR
lightY_D(2) <= ((NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND lightG(3) AND
NOT lightY(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND NOT lightG(3) AND
lightY(3)));
FTCPE_lightY3: FTCPE port map (lightY(3),lightY_T(3),div_cnt(24),'0',NOT rst);
lightY_T(3) <= ((NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND lightG(3) AND
NOT lightY(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND NOT second(3) AND NOT lightG(3) AND
lightY(3)));
FTCPE_second0: FTCPE port map (second(0),second_T(0),div_cnt(24),'0',NOT rst);
second_T(0) <= ((EXP16_.EXP)
OR (_11_.EXP)
OR (second(0) AND lightG(3) AND NOT lightY(3))
OR (NOT second(0) AND second(1) AND NOT lightY(3))
OR (NOT second(0) AND second(2) AND NOT lightY(3)));
FTCPE_second1: FTCPE port map (second(1),second_T(1),div_cnt(24),'0',NOT rst);
second_T(1) <= ((en_2_OBUF.EXP)
OR (NOT second(0) AND second(1) AND lightG(3) AND NOT lightY(3))
OR (NOT second(0) AND NOT second(1) AND second(2) AND NOT lightY(3))
OR (NOT second(0) AND NOT second(1) AND second(3) AND NOT lightY(3)));
FTCPE_second2: FTCPE port map (second(2),second_T(2),div_cnt(24),NOT rst,'0');
second_T(2) <= ((lightR_3_OBUF.EXP)
OR (NOT second(0) AND NOT second(1) AND second(2) AND lightG(3) AND
NOT lightY(3))
OR (NOT second(0) AND NOT second(1) AND NOT second(2) AND second(3) AND
NOT lightY(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND second(2) AND NOT first(3)));
FTCPE_second3: FTCPE port map (second(3),second_T(3),div_cnt(24),NOT rst,'0');
second_T(3) <= ((NOT second(0) AND NOT second(1) AND NOT second(2) AND second(3) AND
lightG(3) AND NOT lightY(3))
OR (NOT second(0) AND NOT first(0) AND NOT first(1) AND NOT first(2) AND
NOT second(1) AND NOT second(2) AND NOT first(3) AND second(3)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC95144XL-10-TQ144
Pin Signal Pin Signal
No. Name No. Name
1 VCC 73 VCC
2 KPR 74 KPR
3 KPR 75 KPR
4 KPR 76 KPR
5 KPR 77 KPR
6 KPR 78 KPR
7 KPR 79 KPR
8 VCC 80 KPR
9 KPR 81 KPR
10 KPR 82 KPR
11 KPR 83 KPR
12 KPR 84 VCC
13 KPR 85 KPR
14 KPR 86 KPR
15 KPR 87 KPR
16 KPR 88 KPR
17 KPR 89 GND
18 GND 90 GND
19 KPR 91 KPR
20 KPR 92 KPR
21 KPR 93 KPR
22 KPR 94 KPR
23 KPR 95 KPR
24 KPR 96 KPR
25 KPR 97 KPR
26 KPR 98 KPR
27 KPR 99 GND
28 KPR 100 KPR
29 GND 101 KPR
30 KPR 102 KPR
31 KPR 103 KPR
32 KPR 104 KPR
33 lightG<1> 105 KPR
34 lightG<2> 106 dataout<7>
35 KPR 107 dataout<6>
36 GND 108 GND
37 VCC 109 VCC
38 KPR 110 KPR
39 lightG<3> 111 dataout<5>
40 lightG<0> 112 KPR
41 lightY<3> 113 dataout<4>
42 VCC 114 GND
43 lightY<1> 115 dataout<3>
44 lightY<2> 116 dataout<2>
45 lightY<0> 117 KPR
46 KPR 118 dataout<1>
47 GND 119 dataout<0>
48 lightR<0> 120 en<3>
49 lightR<2> 121 KPR
50 lightR<1> 122 TDO
51 lightR<3> 123 GND
52 KPR 124 en<4>
53 KPR 125 en<5>
54 KPR 126 en<2>
55 VCC 127 VCC
56 KPR 128 clk
57 KPR 129 KPR
58 KPR 130 KPR
59 KPR 131 en<0>
60 KPR 132 en<1>
61 KPR 133 en<6>
62 GND 134 en<7>
63 TDI 135 KPR
64 KPR 136 KPR
65 TMS 137 KPR
66 KPR 138 KPR
67 TCK 139 KPR
68 KPR 140 KPR
69 KPR 141 VCC
70 KPR 142 KPR
71 rst 143 KPR
72 GND 144 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc95144xl-10-TQ144
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 54
Pterm Limit : 25
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -