traffic.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

dataout(0) <= '1';


dataout(1) <= ((en_2_OBUF$BUF4.EXP)
	OR (en(0) AND NOT second(1) AND NOT second(2) AND NOT second(3))
	OR (NOT en(1) AND NOT second(1) AND NOT second(2) AND NOT second(3))
	OR (en(0) AND second(0) AND second(1) AND second(2) AND 
	NOT second(3))
	OR (NOT en(0) AND en(1) AND NOT first(1) AND NOT first(2) AND NOT first(3)));


dataout(2)_BUFR <= ((_10_.EXP)
	OR (EXP18_.EXP)
	OR (en(0) AND second(0) AND second(1) AND NOT second(3))
	OR (en(0) AND second(0) AND NOT second(2) AND NOT second(3))
	OR (en(0) AND second(1) AND NOT second(2) AND NOT second(3))
	OR (NOT en(1) AND second(0) AND NOT second(2) AND NOT second(3))
	OR (NOT en(1) AND second(1) AND NOT second(2) AND NOT second(3)));


dataout(2) <= dataout(2)_BUFR;


dataout(3) <= ((_12_.EXP)
	OR (en_2_OBUF$BUF5.EXP)
	OR (en(0) AND second(0) AND NOT second(3))
	OR (NOT en(1) AND second(0) AND NOT second(3))
	OR (en(0) AND second(0) AND NOT second(1) AND NOT second(2))
	OR (en(0) AND NOT second(1) AND second(2) AND NOT second(3))
	OR (NOT en(1) AND NOT second(1) AND second(2) AND NOT second(3)));


dataout(4) <= dataout(4)_BUFR;


dataout(4)_BUFR <= ((en_2_OBUF$BUF2.EXP)
	OR (en_2_OBUF$BUF1.EXP)
	OR (en(0) AND second(0) AND second(1) AND second(2))
	OR (en(0) AND second(0) AND NOT second(1) AND NOT second(2))
	OR (NOT en(1) AND second(0) AND second(1) AND second(2))
	OR (NOT en(1) AND second(0) AND NOT second(1) AND NOT second(2))
	OR (en(0) AND NOT second(0) AND second(1) AND NOT second(2) AND 
	second(3)));


dataout(5) <= ((EXP14_.EXP)
	OR (EXP15_.EXP)
	OR (en(0) AND NOT second(0) AND second(2) AND second(3))
	OR (en(0) AND second(1) AND second(2) AND second(3))
	OR (NOT en(1) AND NOT second(0) AND second(2) AND second(3))
	OR (NOT en(1) AND second(1) AND second(2) AND second(3))
	OR (NOT en(0) AND en(1) AND first(1) AND first(2) AND first(3)));


dataout(6) <= ((EXP19_.EXP)
	OR (div_cnt(1).EXP)
	OR (en(0) AND second(0) AND second(1) AND second(3))
	OR (en(0) AND NOT second(0) AND second(1) AND second(2))
	OR (en(0) AND NOT second(0) AND second(2) AND second(3))
	OR (NOT en(1) AND second(0) AND second(1) AND second(3))
	OR (NOT en(1) AND NOT second(0) AND second(1) AND second(2)));


dataout(7) <= dataout(7)_BUFR;


dataout(7)_BUFR <= ((en_2_OBUF$BUF3.EXP)
	OR (EXP17_.EXP)
	OR (en(0) AND second(0) AND second(1) AND NOT second(2) AND 
	second(3))
	OR (en(0) AND second(0) AND NOT second(1) AND second(2) AND 
	second(3))
	OR (en(0) AND second(0) AND NOT second(1) AND NOT second(2) AND 
	NOT second(3))
	OR (NOT en(1) AND second(0) AND second(1) AND NOT second(2) AND 
	second(3))
	OR (NOT en(1) AND second(0) AND NOT second(1) AND second(2) AND 
	second(3)));

FTCPE_div_cnt0: FTCPE port map (div_cnt(0),'1',clk,NOT rst,'0');

FTCPE_div_cnt1: FTCPE port map (div_cnt(1),div_cnt(0),clk,NOT rst,'0');

FTCPE_div_cnt2: FTCPE port map (div_cnt(2),div_cnt_T(2),clk,NOT rst,'0');
div_cnt_T(2) <= (div_cnt(0) AND div_cnt(1));

FTCPE_div_cnt3: FTCPE port map (div_cnt(3),div_cnt_T(3),clk,NOT rst,'0');
div_cnt_T(3) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2));

FTCPE_div_cnt4: FTCPE port map (div_cnt(4),div_cnt_T(4),clk,NOT rst,'0');
div_cnt_T(4) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3));

FTCPE_div_cnt5: FTCPE port map (div_cnt(5),div_cnt_T(5),clk,NOT rst,'0');
div_cnt_T(5) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4));

FTCPE_div_cnt6: FTCPE port map (div_cnt(6),div_cnt_T(6),clk,NOT rst,'0');
div_cnt_T(6) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5));

FTCPE_div_cnt7: FTCPE port map (div_cnt(7),div_cnt_T(7),clk,NOT rst,'0');
div_cnt_T(7) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6));

FTCPE_div_cnt8: FTCPE port map (div_cnt(8),div_cnt_T(8),clk,NOT rst,'0');
div_cnt_T(8) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND 
	div_cnt(7));

FTCPE_div_cnt9: FTCPE port map (div_cnt(9),div_cnt_T(9),clk,NOT rst,'0');
div_cnt_T(9) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND 
	div_cnt(7) AND div_cnt(8));

FTCPE_div_cnt10: FTCPE port map (div_cnt(10),div_cnt_T(10),clk,NOT rst,'0');
div_cnt_T(10) <= (div_cnt(0) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND 
	div_cnt(7) AND div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt11: FTCPE port map (div_cnt(11),div_cnt_T(11),clk,NOT rst,'0');
div_cnt_T(11) <= (div_cnt(0) AND div_cnt(10) AND div_cnt(1) AND 
	div_cnt(2) AND div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND 
	div_cnt(6) AND div_cnt(7) AND div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt12: FTCPE port map (div_cnt(12),div_cnt_T(12),clk,NOT rst,'0');
div_cnt_T(12) <= (div_cnt(0) AND div_cnt(10) AND div_cnt(11) AND 
	div_cnt(1) AND div_cnt(2) AND div_cnt(3) AND div_cnt(4) AND 
	div_cnt(5) AND div_cnt(6) AND div_cnt(7) AND div_cnt(8) AND 
	div_cnt(9));

FTCPE_div_cnt13: FTCPE port map (div_cnt(13),div_cnt_T(13),clk,NOT rst,'0');
div_cnt_T(13) <= (div_cnt(0) AND div_cnt(10) AND div_cnt(11) AND 
	div_cnt(12) AND div_cnt(1) AND div_cnt(2) AND div_cnt(3) AND 
	div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND div_cnt(7) AND 
	div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt14: FTCPE port map (div_cnt(14),div_cnt_T(14),clk,NOT rst,'0');
div_cnt_T(14) <= (div_cnt(0) AND div_cnt(10) AND div_cnt(11) AND 
	div_cnt(12) AND div_cnt(13) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND 
	div_cnt(7) AND div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt15: FTCPE port map (div_cnt(15),div_cnt_T(15),clk,NOT rst,'0');
div_cnt_T(15) <= (div_cnt(0) AND div_cnt(10) AND div_cnt(11) AND 
	div_cnt(12) AND div_cnt(13) AND div_cnt(14) AND div_cnt(1) AND 
	div_cnt(2) AND div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND 
	div_cnt(6) AND div_cnt(7) AND div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt16: FTCPE port map (div_cnt(16),div_cnt_T(16),clk,NOT rst,'0');
div_cnt_T(16) <= (div_cnt(15) AND div_cnt(0) AND div_cnt(10) AND 
	div_cnt(11) AND div_cnt(12) AND div_cnt(13) AND div_cnt(14) AND 
	div_cnt(1) AND div_cnt(2) AND div_cnt(3) AND div_cnt(4) AND 
	div_cnt(5) AND div_cnt(6) AND div_cnt(7) AND div_cnt(8) AND 
	div_cnt(9));

FTCPE_div_cnt17: FTCPE port map (div_cnt(17),div_cnt_T(17),clk,NOT rst,'0');
div_cnt_T(17) <= (div_cnt(15) AND div_cnt(0) AND div_cnt(10) AND 
	div_cnt(11) AND div_cnt(12) AND div_cnt(13) AND div_cnt(14) AND 
	div_cnt(16) AND div_cnt(1) AND div_cnt(2) AND div_cnt(3) AND 
	div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND div_cnt(7) AND 
	div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt18: FTCPE port map (div_cnt(18),div_cnt_T(18),clk,NOT rst,'0');
div_cnt_T(18) <= (div_cnt(15) AND div_cnt(0) AND div_cnt(10) AND 
	div_cnt(11) AND div_cnt(12) AND div_cnt(13) AND div_cnt(14) AND 
	div_cnt(16) AND div_cnt(17) AND div_cnt(1) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND 
	div_cnt(7) AND div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt19: FTCPE port map (div_cnt(19),div_cnt_T(19),clk,NOT rst,'0');
div_cnt_T(19) <= (div_cnt(15) AND div_cnt(0) AND div_cnt(10) AND 
	div_cnt(11) AND div_cnt(12) AND div_cnt(13) AND div_cnt(14) AND 
	div_cnt(16) AND div_cnt(17) AND div_cnt(18) AND div_cnt(1) AND 
	div_cnt(2) AND div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND 
	div_cnt(6) AND div_cnt(7) AND div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt20: FTCPE port map (div_cnt(20),div_cnt_T(20),clk,NOT rst,'0');
div_cnt_T(20) <= (div_cnt(15) AND div_cnt(0) AND div_cnt(10) AND 
	div_cnt(11) AND div_cnt(12) AND div_cnt(13) AND div_cnt(14) AND 
	div_cnt(16) AND div_cnt(17) AND div_cnt(18) AND div_cnt(19) AND 
	div_cnt(1) AND div_cnt(2) AND div_cnt(3) AND div_cnt(4) AND 
	div_cnt(5) AND div_cnt(6) AND div_cnt(7) AND div_cnt(8) AND 
	div_cnt(9));

FTCPE_div_cnt21: FTCPE port map (div_cnt(21),div_cnt_T(21),clk,NOT rst,'0');
div_cnt_T(21) <= (div_cnt(15) AND div_cnt(0) AND div_cnt(10) AND 
	div_cnt(11) AND div_cnt(12) AND div_cnt(13) AND div_cnt(14) AND 
	div_cnt(16) AND div_cnt(17) AND div_cnt(18) AND div_cnt(19) AND 
	div_cnt(1) AND div_cnt(20) AND div_cnt(2) AND div_cnt(3) AND 
	div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND div_cnt(7) AND 
	div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt22: FTCPE port map (div_cnt(22),div_cnt_T(22),clk,NOT rst,'0');
div_cnt_T(22) <= (div_cnt(15) AND div_cnt(0) AND div_cnt(10) AND 
	div_cnt(11) AND div_cnt(12) AND div_cnt(13) AND div_cnt(14) AND 
	div_cnt(16) AND div_cnt(17) AND div_cnt(18) AND div_cnt(19) AND 
	div_cnt(1) AND div_cnt(20) AND div_cnt(21) AND div_cnt(2) AND 
	div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND div_cnt(6) AND 
	div_cnt(7) AND div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt23: FTCPE port map (div_cnt(23),div_cnt_T(23),clk,NOT rst,'0');
div_cnt_T(23) <= (div_cnt(15) AND div_cnt(0) AND div_cnt(10) AND 
	div_cnt(11) AND div_cnt(12) AND div_cnt(13) AND div_cnt(14) AND 
	div_cnt(16) AND div_cnt(17) AND div_cnt(18) AND div_cnt(19) AND 
	div_cnt(1) AND div_cnt(20) AND div_cnt(21) AND div_cnt(22) AND 
	div_cnt(2) AND div_cnt(3) AND div_cnt(4) AND div_cnt(5) AND 
	div_cnt(6) AND div_cnt(7) AND div_cnt(8) AND div_cnt(9));

FTCPE_div_cnt24: FTCPE port map (div_cnt(24),div_cnt_T(24),clk,NOT rst,'0');
div_cnt_T(24) <= (div_cnt(15) AND div_cnt(0) AND div_cnt(10) AND 
	div_cnt(11) AND div_cnt(12) AND div_cnt(13) AND div_cnt(14) AND 
	div_cnt(16) AND div_cnt(17) AND div_cnt(18) AND div_cnt(19) AND 
	div_cnt(1) AND div_cnt(20) AND div_cnt(21) AND div_cnt(22) AND 
	div_cnt(23) AND div_cnt(2) AND div_cnt(3) AND div_cnt(4) AND 
	div_cnt(5) AND div_cnt(6) AND div_cnt(7) AND div_cnt(8) AND 
	div_cnt(9));

FTCPE_en0: FTCPE port map (en(0),'1',div_cnt(15),NOT rst,'0');

FTCPE_en1: FTCPE port map (en(1),'1',div_cnt(15),'0',NOT rst);


en(2) <= en_2_OBUF$BUF0.EXP;


en(3) <= '1';


en(4) <= '1';


en(5) <= '1';


en(6) <= '1';


en(7) <= en_xhdl(1).EXP;

FDCPE_first0: FDCPE port map (first(0),first_D(0),div_cnt(24),NOT rst,'0');
first_D(0) <= ((first(0) AND lightY(3))
	OR (NOT second(0) AND first(0) AND NOT second(1) AND NOT second(2) AND 
	NOT second(3))
	OR (NOT second(0) AND NOT first(1) AND NOT first(2) AND NOT second(1) AND 
	NOT second(2) AND NOT first(3) AND NOT second(3) AND lightG(3)));