traffic.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

 
cpldfit:  version H.42                              Xilinx Inc.
                                  Fitter Report
Design Name: traffic                             Date:  2-21-2006, 11:58AM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
64 /144 ( 44%) 265 /720  ( 37%) 121/432 ( 28%)   43 /144 ( 30%) 30 /117 ( 26%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          10/18       26/54       30/90       0/15
FB2           0/18        0/54        0/90       0/15
FB3          18/18*      26/54       66/90      12/15
FB4          17/18       26/54       74/90       6/15
FB5           0/18        0/54        0/90       0/14
FB6          13/18       17/54       69/90       9/13
FB7           0/18        0/54        0/90       0/15
FB8           6/18       26/54       26/90       1/15
             -----       -----       -----      -----    
             64/144     121/432     265/720     28/117

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    2           2    |  I/O              :    30     109
Output        :   28          28    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     0       4
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     30          30

** Power Data **

There are 64 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal dataout<7> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal dataout<4> to allow all signals assigned to this function block to be
   placed.
WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal dataout<2> to allow all signals assigned to this function block to be
   placed.
*************************  Summary of Mapped Logic  ************************

** 28 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
lightG<3>           4     12    FB3_1   39   I/O     O       STD  FAST SET
lightY<3>           4     12    FB3_3   41   I/O     O       STD  FAST SET
lightY<2>           5     12    FB3_4   44   I/O     O       STD  FAST SET
lightG<1>           5     12    FB3_5   33   I/O     O       STD  FAST SET
lightG<2>           5     12    FB3_6   34   I/O     O       STD  FAST SET
lightG<0>           5     12    FB3_9   40   I/O     O       STD  FAST SET
lightR<0>           1     2     FB3_10  48   I/O     O       STD  FAST 
lightY<1>           5     12    FB3_11  43   I/O     O       STD  FAST SET
lightY<0>           5     12    FB3_12  45   I/O     O       STD  FAST SET
lightR<2>           1     2     FB3_14  49   I/O     O       STD  FAST 
lightR<1>           1     2     FB3_15  50   I/O     O       STD  FAST 
lightR<3>           1     2     FB3_17  51   I/O     O       STD  FAST 
dataout<1>          9     10    FB4_1   118  I/O     O       STD  FAST 
en<2>               1     0     FB4_2   126  I/O     O       STD  FAST 
en<6>               0     0     FB4_3   133  I/O     O       STD  FAST 
en<0>               2     2     FB4_9   131  I/O     O       STD  FAST RESET
en<1>               2     2     FB4_11  132  I/O     O       STD  FAST RESET
en<7>               1     0     FB4_12  134  I/O     O       STD  FAST 
dataout<7>          1     1     FB6_2   106  I/O     O       STD  FAST 
dataout<5>          9     10    FB6_4   111  I/O     O       STD  FAST 
dataout<4>          1     1     FB6_8   113  I/O     O       STD  FAST 
dataout<2>          1     1     FB6_9   116  I/O     O       STD  FAST 
dataout<3>          9     10    FB6_10  115  I/O     O       STD  FAST 
dataout<0>          0     0     FB6_11  119  I/O     O       STD  FAST 
en<3>               0     0     FB6_12  120  I/O     O       STD  FAST 
en<4>               0     0     FB6_15  124  I/O     O       STD  FAST 
en<5>               0     0     FB6_17  125  I/O     O       STD  FAST 
dataout<6>          12    10    FB8_16  107  I/O     O       STD  FAST 

** 36 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
div_cnt<24>         3     26    FB1_9   STD  RESET
div_cnt<23>         3     25    FB1_10  STD  RESET
div_cnt<22>         3     24    FB1_11  STD  RESET
div_cnt<21>         3     23    FB1_12  STD  RESET
div_cnt<20>         3     22    FB1_13  STD  RESET
div_cnt<19>         3     21    FB1_14  STD  RESET
div_cnt<18>         3     20    FB1_15  STD  RESET
div_cnt<17>         3     19    FB1_16  STD  RESET
div_cnt<16>         3     18    FB1_17  STD  RESET
div_cnt<15>         3     17    FB1_18  STD  RESET
div_cnt<13>         3     15    FB3_2   STD  RESET
div_cnt<12>         3     14    FB3_7   STD  RESET
div_cnt<11>         3     13    FB3_8   STD  RESET
second<3>           4     12    FB3_13  STD  RESET
first<0>            5     12    FB3_16  STD  RESET
second<2>           6     12    FB3_18  STD  RESET
div_cnt<7>          3     9     FB4_4   STD  RESET
div_cnt<6>          3     8     FB4_5   STD  RESET
div_cnt<5>          3     7     FB4_6   STD  RESET
div_cnt<4>          3     6     FB4_7   STD  RESET
div_cnt<10>         3     12    FB4_8   STD  RESET
first<3>            8     11    FB4_10  STD  RESET
second<1>           10    12    FB4_13  STD  RESET
div_cnt<8>          3     10    FB4_14  STD  RESET
first<1>            9     12    FB4_15  STD  RESET
div_cnt<9>          3     11    FB4_16  STD  RESET
first<2>            11    12    FB4_18  STD  RESET
dataout<2>_BUFR     12    10    FB6_1   STD  
second<0>           12    12    FB6_7   STD  RESET
dataout<7>_BUFR     12    10    FB6_13  STD  
dataout<4>_BUFR     12    10    FB6_16  STD  
div_cnt<0>          2     2     FB8_12  STD  RESET
div_cnt<3>          3     5     FB8_13  STD  RESET
div_cnt<2>          3     4     FB8_14  STD  RESET
div_cnt<1>          3     3     FB8_17  STD  RESET
div_cnt<14>         3     16    FB8_18  STD  RESET

** 2 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
clk                 FB4_5   128  I/O     I
rst                 FB7_2   71   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1   23    I/O     
(unused)              0       0     0   5     FB1_2   16    I/O     
(unused)              0       0     0   5     FB1_3   17    I/O     
(unused)              0       0     0   5     FB1_4   25    I/O     
(unused)              0       0     0   5     FB1_5   19    I/O     
(unused)              0       0     0   5     FB1_6   20    I/O     
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   21    I/O     
div_cnt<24>           3       0     0   2     FB1_9   22    I/O     (b)
div_cnt<23>           3       0     0   2     FB1_10  31    I/O     (b)
div_cnt<22>           3       0     0   2     FB1_11  24    I/O     (b)
div_cnt<21>           3       0     0   2     FB1_12  26    I/O     (b)
div_cnt<20>           3       0     0   2     FB1_13        (b)     (b)
div_cnt<19>           3       0     0   2     FB1_14  27    I/O     (b)
div_cnt<18>           3       0     0   2     FB1_15  28    I/O     (b)
div_cnt<17>           3       0     0   2     FB1_16  35    I/O     (b)
div_cnt<16>           3       0     0   2     FB1_17  30    GCK/I/O (b)
div_cnt<15>           3       0     0   2     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: clk               10: div_cnt<17>       19: div_cnt<3> 
  2: div_cnt<0>        11: div_cnt<18>       20: div_cnt<4> 
  3: div_cnt<10>       12: div_cnt<19>       21: div_cnt<5> 
  4: div_cnt<11>       13: div_cnt<1>        22: div_cnt<6> 
  5: div_cnt<12>       14: div_cnt<20>       23: div_cnt<7> 
  6: div_cnt<13>       15: div_cnt<21>       24: div_cnt<8> 
  7: div_cnt<14>       16: div_cnt<22>       25: div_cnt<9> 
  8: div_cnt<15>       17: div_cnt<23>       26: rst 
  9: div_cnt<16>       18: div_cnt<2>       

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
div_cnt<24>          XXXXXXXXXXXXXXXXXXXXXXXXXX.............. 26
div_cnt<23>          XXXXXXXXXXXXXXXX.XXXXXXXXX.............. 25
div_cnt<22>          XXXXXXXXXXXXXXX..XXXXXXXXX.............. 24
div_cnt<21>          XXXXXXXXXXXXXX...XXXXXXXXX.............. 23
div_cnt<20>          XXXXXXXXXXXXX....XXXXXXXXX.............. 22
div_cnt<19>          XXXXXXXXXXX.X....XXXXXXXXX.............. 21
div_cnt<18>          XXXXXXXXXX..X....XXXXXXXXX.............. 20
div_cnt<17>          XXXXXXXXX...X....XXXXXXXXX.............. 19
div_cnt<16>          XXXXXXXX....X....XXXXXXXXX.............. 18
div_cnt<15>          XXXXXXX.....X....XXXXXXXXX.............. 17
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1   142   I/O     
(unused)              0       0     0   5     FB2_2   143   GSR/I/O 
(unused)              0       0     0   5     FB2_3         (b)     
(unused)              0       0     0   5     FB2_4   4     I/O     
(unused)              0       0     0   5     FB2_5   2     GTS/I/O 
(unused)              0       0     0   5     FB2_6   3     GTS/I/O 
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   5     GTS/I/O 
(unused)              0       0     0   5     FB2_9   6     GTS/I/O 
(unused)              0       0     0   5     FB2_10  7     I/O     
(unused)              0       0     0   5     FB2_11  9     I/O     
(unused)              0       0     0   5     FB2_12  10    I/O     
(unused)              0       0     0   5     FB2_13  12    I/O     
(unused)              0       0     0   5     FB2_14  11    I/O     
(unused)              0       0     0   5     FB2_15  13    I/O     
(unused)              0       0     0   5     FB2_16  14    I/O     
(unused)              0       0     0   5     FB2_17  15    I/O     
(unused)              0       0     0   5     FB2_18        (b)     
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               26/28
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
lightG<3>             4       0     0   1     FB3_1   39    I/O     O
div_cnt<13>           3       0     0   2     FB3_2   32    GCK/I/O (b)
lightY<3>             4       0     0   1     FB3_3   41    I/O     O
lightY<2>             5       0     0   0     FB3_4   44    I/O     O
lightG<1>             5       0     0   0     FB3_5   33    I/O     O
lightG<2>             5       0     0   0     FB3_6   34    I/O     O
div_cnt<12>           3       0     0   2     FB3_7   46    I/O     (b)
div_cnt<11>           3       0     0   2     FB3_8   38    GCK/I/O (b)
lightG<0>             5       0     0   0     FB3_9   40    I/O     O