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📄 traffic.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
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   div_cnt<13>.T = div_cnt<0> & div_cnt<10> & div_cnt<11> & 
	div_cnt<12> & div_cnt<1> & div_cnt<2> & div_cnt<3> & 
	div_cnt<4> & div_cnt<5> & div_cnt<6> & div_cnt<7> & 
	div_cnt<8> & div_cnt<9>;
   div_cnt<13>.CLK = clk;
   div_cnt<13>.AR = !rst;

MACROCELL | 7 | 17 | div_cnt<14>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 10 | 0 | 8 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9
INPUTS | 16 | div_cnt<0>  | div_cnt<10>  | div_cnt<11>  | div_cnt<12>  | div_cnt<13>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | div_cnt<8>  | div_cnt<9>  | clk  | rst
INPUTMC | 14 | 7 | 11 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTP | 2 | 143 | 79
EQ | 6 | 
   div_cnt<14>.T = div_cnt<0> & div_cnt<10> & div_cnt<11> & 
	div_cnt<12> & div_cnt<13> & div_cnt<1> & div_cnt<2> & 
	div_cnt<3> & div_cnt<4> & div_cnt<5> & div_cnt<6> & 
	div_cnt<7> & div_cnt<8> & div_cnt<9>;
   div_cnt<14>.CLK = clk;
   div_cnt<14>.AR = !rst;

MACROCELL | 0 | 16 | div_cnt<16>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 8 | 0 | 8 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9
INPUTS | 18 | div_cnt<15>  | div_cnt<0>  | div_cnt<10>  | div_cnt<11>  | div_cnt<12>  | div_cnt<13>  | div_cnt<14>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | div_cnt<8>  | div_cnt<9>  | clk  | rst
INPUTMC | 16 | 0 | 17 | 7 | 11 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTP | 2 | 143 | 79
EQ | 7 | 
   div_cnt<16>.T = div_cnt<15> & div_cnt<0> & div_cnt<10> & 
	div_cnt<11> & div_cnt<12> & div_cnt<13> & div_cnt<14> & 
	div_cnt<1> & div_cnt<2> & div_cnt<3> & div_cnt<4> & 
	div_cnt<5> & div_cnt<6> & div_cnt<7> & div_cnt<8> & 
	div_cnt<9>;
   div_cnt<16>.CLK = clk;
   div_cnt<16>.AR = !rst;

MACROCELL | 0 | 15 | div_cnt<17>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 7 | 0 | 8 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9
INPUTS | 19 | div_cnt<15>  | div_cnt<0>  | div_cnt<10>  | div_cnt<11>  | div_cnt<12>  | div_cnt<13>  | div_cnt<14>  | div_cnt<16>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | div_cnt<8>  | div_cnt<9>  | clk  | rst
INPUTMC | 17 | 0 | 17 | 7 | 11 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTP | 2 | 143 | 79
EQ | 7 | 
   div_cnt<17>.T = div_cnt<15> & div_cnt<0> & div_cnt<10> & 
	div_cnt<11> & div_cnt<12> & div_cnt<13> & div_cnt<14> & 
	div_cnt<16> & div_cnt<1> & div_cnt<2> & div_cnt<3> & 
	div_cnt<4> & div_cnt<5> & div_cnt<6> & div_cnt<7> & 
	div_cnt<8> & div_cnt<9>;
   div_cnt<17>.CLK = clk;
   div_cnt<17>.AR = !rst;

MACROCELL | 0 | 14 | div_cnt<18>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 6 | 0 | 8 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9
INPUTS | 20 | div_cnt<15>  | div_cnt<0>  | div_cnt<10>  | div_cnt<11>  | div_cnt<12>  | div_cnt<13>  | div_cnt<14>  | div_cnt<16>  | div_cnt<17>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | div_cnt<8>  | div_cnt<9>  | clk  | rst
INPUTMC | 18 | 0 | 17 | 7 | 11 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTP | 2 | 143 | 79
EQ | 7 | 
   div_cnt<18>.T = div_cnt<15> & div_cnt<0> & div_cnt<10> & 
	div_cnt<11> & div_cnt<12> & div_cnt<13> & div_cnt<14> & 
	div_cnt<16> & div_cnt<17> & div_cnt<1> & div_cnt<2> & 
	div_cnt<3> & div_cnt<4> & div_cnt<5> & div_cnt<6> & 
	div_cnt<7> & div_cnt<8> & div_cnt<9>;
   div_cnt<18>.CLK = clk;
   div_cnt<18>.AR = !rst;

MACROCELL | 0 | 13 | div_cnt<19>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 5 | 0 | 8 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9
INPUTS | 21 | div_cnt<15>  | div_cnt<0>  | div_cnt<10>  | div_cnt<11>  | div_cnt<12>  | div_cnt<13>  | div_cnt<14>  | div_cnt<16>  | div_cnt<17>  | div_cnt<18>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | div_cnt<8>  | div_cnt<9>  | clk  | rst
INPUTMC | 19 | 0 | 17 | 7 | 11 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTP | 2 | 143 | 79
EQ | 7 | 
   div_cnt<19>.T = div_cnt<15> & div_cnt<0> & div_cnt<10> & 
	div_cnt<11> & div_cnt<12> & div_cnt<13> & div_cnt<14> & 
	div_cnt<16> & div_cnt<17> & div_cnt<18> & div_cnt<1> & 
	div_cnt<2> & div_cnt<3> & div_cnt<4> & div_cnt<5> & 
	div_cnt<6> & div_cnt<7> & div_cnt<8> & div_cnt<9>;
   div_cnt<19>.CLK = clk;
   div_cnt<19>.AR = !rst;

MACROCELL | 7 | 16 | div_cnt<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 24 | 0 | 8 | 0 | 17 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15 | 7 | 15
INPUTS | 9 | div_cnt<0>  | clk  | rst  | en<0>  | en<1>  | first<0>  | first<2>  | first<3>  | first<1>
INPUTMC | 7 | 7 | 11 | 3 | 8 | 3 | 10 | 2 | 15 | 3 | 17 | 3 | 9 | 3 | 14
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 7 | 15
EQ | 6 | 
   div_cnt<1>.T = div_cnt<0>;
   div_cnt<1>.CLK = clk;
   div_cnt<1>.AR = !rst;
    div_cnt<1>.EXP  =  !en<0> & en<1> & !first<0> & first<2> & first<3>
	# !en<0> & en<1> & first<0> & !first<1> & first<2> & 
	!first<3>

MACROCELL | 0 | 12 | div_cnt<20>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 4 | 0 | 8 | 0 | 11 | 0 | 10 | 0 | 9
INPUTS | 22 | div_cnt<15>  | div_cnt<0>  | div_cnt<10>  | div_cnt<11>  | div_cnt<12>  | div_cnt<13>  | div_cnt<14>  | div_cnt<16>  | div_cnt<17>  | div_cnt<18>  | div_cnt<19>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | div_cnt<8>  | div_cnt<9>  | clk  | rst
INPUTMC | 20 | 0 | 17 | 7 | 11 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTP | 2 | 143 | 79
EQ | 8 | 
   div_cnt<20>.T = div_cnt<15> & div_cnt<0> & div_cnt<10> & 
	div_cnt<11> & div_cnt<12> & div_cnt<13> & div_cnt<14> & 
	div_cnt<16> & div_cnt<17> & div_cnt<18> & div_cnt<19> & 
	div_cnt<1> & div_cnt<2> & div_cnt<3> & div_cnt<4> & 
	div_cnt<5> & div_cnt<6> & div_cnt<7> & div_cnt<8> & 
	div_cnt<9>;
   div_cnt<20>.CLK = clk;
   div_cnt<20>.AR = !rst;

MACROCELL | 0 | 11 | div_cnt<21>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 3 | 0 | 8 | 0 | 10 | 0 | 9
INPUTS | 23 | div_cnt<15>  | div_cnt<0>  | div_cnt<10>  | div_cnt<11>  | div_cnt<12>  | div_cnt<13>  | div_cnt<14>  | div_cnt<16>  | div_cnt<17>  | div_cnt<18>  | div_cnt<19>  | div_cnt<1>  | div_cnt<20>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | div_cnt<8>  | div_cnt<9>  | clk  | rst
INPUTMC | 21 | 0 | 17 | 7 | 11 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 7 | 16 | 0 | 12 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTP | 2 | 143 | 79
EQ | 8 | 
   div_cnt<21>.T = div_cnt<15> & div_cnt<0> & div_cnt<10> & 
	div_cnt<11> & div_cnt<12> & div_cnt<13> & div_cnt<14> & 
	div_cnt<16> & div_cnt<17> & div_cnt<18> & div_cnt<19> & 
	div_cnt<1> & div_cnt<20> & div_cnt<2> & div_cnt<3> & 
	div_cnt<4> & div_cnt<5> & div_cnt<6> & div_cnt<7> & 
	div_cnt<8> & div_cnt<9>;
   div_cnt<21>.CLK = clk;
   div_cnt<21>.AR = !rst;

MACROCELL | 0 | 10 | div_cnt<22>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 2 | 0 | 8 | 0 | 9
INPUTS | 24 | div_cnt<15>  | div_cnt<0>  | div_cnt<10>  | div_cnt<11>  | div_cnt<12>  | div_cnt<13>  | div_cnt<14>  | div_cnt<16>  | div_cnt<17>  | div_cnt<18>  | div_cnt<19>  | div_cnt<1>  | div_cnt<20>  | div_cnt<21>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | div_cnt<8>  | div_cnt<9>  | clk  | rst
INPUTMC | 22 | 0 | 17 | 7 | 11 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 7 | 16 | 0 | 12 | 0 | 11 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTP | 2 | 143 | 79
EQ | 8 | 
   div_cnt<22>.T = div_cnt<15> & div_cnt<0> & div_cnt<10> & 
	div_cnt<11> & div_cnt<12> & div_cnt<13> & div_cnt<14> & 
	div_cnt<16> & div_cnt<17> & div_cnt<18> & div_cnt<19> & 
	div_cnt<1> & div_cnt<20> & div_cnt<21> & div_cnt<2> & 
	div_cnt<3> & div_cnt<4> & div_cnt<5> & div_cnt<6> & 
	div_cnt<7> & div_cnt<8> & div_cnt<9>;
   div_cnt<22>.CLK = clk;
   div_cnt<22>.AR = !rst;

MACROCELL | 0 | 9 | div_cnt<23>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 1 | 0 | 8
INPUTS | 25 | div_cnt<15>  | div_cnt<0>  | div_cnt<10>  | div_cnt<11>  | div_cnt<12>  | div_cnt<13>  | div_cnt<14>  | div_cnt<16>  | div_cnt<17>  | div_cnt<18>  | div_cnt<19>  | div_cnt<1>  | div_cnt<20>  | div_cnt<21>  | div_cnt<22>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | div_cnt<8>  | div_cnt<9>  | clk  | rst
INPUTMC | 23 | 0 | 17 | 7 | 11 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 7 | 16 | 0 | 12 | 0 | 11 | 0 | 10 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTP | 2 | 143 | 79
EQ | 8 | 
   div_cnt<23>.T = div_cnt<15> & div_cnt<0> & div_cnt<10> & 
	div_cnt<11> & div_cnt<12> & div_cnt<13> & div_cnt<14> & 
	div_cnt<16> & div_cnt<17> & div_cnt<18> & div_cnt<19> & 
	div_cnt<1> & div_cnt<20> & div_cnt<21> & div_cnt<22> & 
	div_cnt<2> & div_cnt<3> & div_cnt<4> & div_cnt<5> & 
	div_cnt<6> & div_cnt<7> & div_cnt<8> & div_cnt<9>;
   div_cnt<23>.CLK = clk;
   div_cnt<23>.AR = !rst;

MACROCELL | 7 | 13 | div_cnt<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 22 | 0 | 8 | 0 | 17 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTS | 4 | div_cnt<0>  | div_cnt<1>  | clk  | rst
INPUTMC | 2 | 7 | 11 | 7 | 16
INPUTP | 2 | 143 | 79
EQ | 3 | 
   div_cnt<2>.T = div_cnt<0> & div_cnt<1>;
   div_cnt<2>.CLK = clk;
   div_cnt<2>.AR = !rst;

MACROCELL | 7 | 12 | div_cnt<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 21 | 0 | 8 | 0 | 17 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTS | 5 | div_cnt<0>  | div_cnt<1>  | div_cnt<2>  | clk  | rst
INPUTMC | 3 | 7 | 11 | 7 | 16 | 7 | 13
INPUTP | 2 | 143 | 79
EQ | 3 | 
   div_cnt<3>.T = div_cnt<0> & div_cnt<1> & div_cnt<2>;
   div_cnt<3>.CLK = clk;
   div_cnt<3>.AR = !rst;

MACROCELL | 3 | 6 | div_cnt<4>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 20 | 0 | 8 | 0 | 17 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTS | 6 | div_cnt<0>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | clk  | rst
INPUTMC | 4 | 7 | 11 | 7 | 16 | 7 | 13 | 7 | 12
INPUTP | 2 | 143 | 79
EQ | 4 | 
   div_cnt<4>.T = div_cnt<0> & div_cnt<1> & div_cnt<2> & 
	div_cnt<3>;
   div_cnt<4>.CLK = clk;
   div_cnt<4>.AR = !rst;

MACROCELL | 3 | 5 | div_cnt<5>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 19 | 0 | 8 | 0 | 17 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 3 | 4 | 3 | 3 | 3 | 13 | 3 | 15
INPUTS | 7 | div_cnt<0>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | clk  | rst
INPUTMC | 5 | 7 | 11 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6
INPUTP | 2 | 143 | 79
EQ | 4 | 
   div_cnt<5>.T = div_cnt<0> & div_cnt<1> & div_cnt<2> & 
	div_cnt<3> & div_cnt<4>;
   div_cnt<5>.CLK = clk;
   div_cnt<5>.AR = !rst;

MACROCELL | 3 | 4 | div_cnt<6>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 18 | 0 | 8 | 0 | 17 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 3 | 3 | 3 | 13 | 3 | 15
INPUTS | 8 | div_cnt<0>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | clk  | rst
INPUTMC | 6 | 7 | 11 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5
INPUTP | 2 | 143 | 79
EQ | 4 | 
   div_cnt<6>.T = div_cnt<0> & div_cnt<1> & div_cnt<2> & 
	div_cnt<3> & div_cnt<4> & div_cnt<5>;
   div_cnt<6>.CLK = clk;
   div_cnt<6>.AR = !rst;

MACROCELL | 3 | 3 | div_cnt<7>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 17 | 0 | 8 | 0 | 17 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 3 | 13 | 3 | 15
INPUTS | 9 | div_cnt<0>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | clk  | rst
INPUTMC | 7 | 7 | 11 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4
INPUTP | 2 | 143 | 79
EQ | 4 | 
   div_cnt<7>.T = div_cnt<0> & div_cnt<1> & div_cnt<2> & 
	div_cnt<3> & div_cnt<4> & div_cnt<5> & div_cnt<6>;
   div_cnt<7>.CLK = clk;
   div_cnt<7>.AR = !rst;

MACROCELL | 3 | 13 | div_cnt<8>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 17 | 0 | 8 | 0 | 17 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 3 | 15 | 3 | 14
INPUTS | 14 | div_cnt<0>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | clk  | rst  | second<1>  | lightG<3>  | lightY<3>  | second<2>
INPUTMC | 12 | 7 | 11 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 12 | 2 | 0 | 2 | 2 | 2 | 17
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 3 | 14
EQ | 7 | 
   div_cnt<8>.T = div_cnt<0> & div_cnt<1> & div_cnt<2> & 
	div_cnt<3> & div_cnt<4> & div_cnt<5> & div_cnt<6> & 
	div_cnt<7>;
   div_cnt<8>.CLK = clk;
   div_cnt<8>.AR = !rst;
    div_cnt<8>.EXP  =  second<1> & lightG<3> & !lightY<3>
	# second<2> & lightG<3> & !lightY<3>

MACROCELL | 3 | 15 | div_cnt<9>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 16 | 0 | 8 | 0 | 17 | 3 | 7 | 2 | 7 | 2 | 6 | 2 | 1 | 7 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 3 | 14
INPUTS | 17 | div_cnt<0>  | div_cnt<1>  | div_cnt<2>  | div_cnt<3>  | div_cnt<4>  | div_cnt<5>  | div_cnt<6>  | div_cnt<7>  | div_cnt<8>  | clk  | rst  | first<0>  | first<2>  | first<3>  | second<3>  | lightG<3>  | lightY<3>
INPUTMC | 15 | 7 | 11 | 7 | 16 | 7 | 13 | 7 | 12 | 3 | 6 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 13 | 2 | 15 | 3 | 17 | 3 | 9 | 2 | 12 | 2 | 0 | 2 | 2
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 3 | 14
EQ | 7 | 
   div_cnt<9>.T = div_cnt<0> & div_cnt<1> & div_cnt<2> & 
	div_cnt<3> & div_cnt<4> & div_cnt<5> & div_cnt<6> & 
	div_cnt<7> & div_cnt<8>;
   div_cnt<9>.CLK = clk;
   div_cnt<9>.AR = !rst;
    div_cnt<9>.EXP  =  !first<0> & !first<2> & !first<3>
	# second<3> & lightG<3> & !lightY<3>

MACROCELL | 3 | 0 | dataout_1_OBUF
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 3 | 17
INPUTS | 12 | en<0>  | second<1>  | second<2>  | second<3>  | en<1>  | first<1>  | first<2>  | first<3>  | second<0>  | lightG<3>  | lightY<3>  | en_2_OBUF$BUF4.EXP
INPUTMC | 12 | 3 | 8 | 3 | 12 | 2 | 17 | 2 | 12 | 3 | 10 | 3 | 14 | 3 | 17 | 3 | 9 | 5 | 6 | 2 | 0 | 2 | 2 | 3 | 1
EXPORTS | 1 | 3 | 17
IMPORTS | 1 | 3 | 1
EQ | 17 | 
   dataout<1> = en<0> & !second<1> & !second<2> & !second<3>
	# !en<1> & !second<1> & !second<2> & !second<3>
	# en<0> & second<0> & second<1> & second<2> & 
	!second<3>
	# !en<0> & en<1> & !first<1> & !first<2> & !first<3>
;Imported pterms FB4_2
	# en<0> & !second<0> & !second<1> & second<2> & 
	second<3>
	# !en<1> & second<0> & second<1> & second<2> & 
	!second<3>
	# !en<1> & !second<0> & !second<1> & second<2> & 
	second<3>
	# !en<0> & en<1> & first<0> & first<1> & first<2> & 
	!first<3>
	# !en<0> & en<1> & !first<0> & !first<1> & first<2> & 
	first<3>;
    dataout_1_OBUF.EXP  =  first<2> & second<3> & lightG<3> & !lightY<3>

MACROCELL | 5 | 0 | dataout<2>_BUFR.MC

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