clock.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

#      1-bit register              : 17
#      15-bit register             : 1
#      26-bit register             : 1
#      3-bit register              : 1
#      4-bit register              : 1
# Counters                         : 4
#      4-bit up counter            : 4
# Multiplexers                     : 3
#      4-bit 4-to-1 multiplexer    : 2
#      4-bit 8-to-1 multiplexer    : 1
# Decoders                         : 1
#      1-of-8 decoder              : 1
# Adders/Subtractors               : 4
#      15-bit adder                : 1
#      26-bit adder                : 1
#      4-bit adder                 : 2
# Comparators                      : 2
#      15-bit comparator lessequal : 1
#      26-bit comparator lessequal : 1

Cell Usage :
# BELS                             : 320
#      GND                         : 1
#      INV                         : 7
#      LUT1                        : 11
#      LUT1_L                      : 36
#      LUT2                        : 14
#      LUT2_D                      : 2
#      LUT2_L                      : 26
#      LUT3                        : 22
#      LUT3_L                      : 5
#      LUT4                        : 39
#      LUT4_D                      : 3
#      LUT4_L                      : 18
#      MUXCY                       : 66
#      MUXF5                       : 10
#      MUXF6                       : 4
#      VCC                         : 1
#      XORCY                       : 55
# FlipFlops/Latches                : 84
#      FDC                         : 52
#      FDCE                        : 3
#      FDCPE                       : 16
#      FDE                         : 4
#      FDP                         : 8
#      FDPE                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 17
#      IBUF                        : 1
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     103  out of    768    13%  
 Number of Slice Flip Flops:            84  out of   1536     5%  
 Number of 4 input LUTs:               176  out of   1536    11%  
 Number of bonded IOBs:                 18  out of     96    18%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_1/qout:Q                      | NONE                   | 15    |
XLXI_17/carry:Q                    | NONE                   | 8     |
XLXI_16/carry:Q                    | NONE                   | 9     |
XLXI_3/qout:Q                      | NONE                   | 9     |
clk                                | BUFGP                  | 43    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 12.225ns (Maximum Frequency: 81.800MHz)
   Minimum input arrival time before clock: 6.396ns
   Maximum output required time after clock: 9.092ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_1/qout:Q'
  Clock period: 8.523ns (frequency: 117.330MHz)
  Total number of paths / destination ports: 74 / 15
-------------------------------------------------------------------------
Delay:               8.523ns (Levels of Logic = 3)
  Source:            XLXI_6/cnt_0 (FF)
  Destination:       XLXI_6/qout_3 (FF)
  Source Clock:      XLXI_1/qout:Q rising
  Destination Clock: XLXI_1/qout:Q rising

  Data Path: XLXI_6/cnt_0 to XLXI_6/qout_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             27   1.085   3.195  XLXI_6/cnt_0 (XLXI_6/cnt_0)
     LUT2_D:I0->O          8   0.549   1.845  XLXI_6/_n0000<1>2 (XLXI_6/_n0000<1>)
     MUXF5:S->O            1   0.824   0.000  XLXI_6/_n0000<1>_rn_6 (XLXI_6/MUX_BLOCK__n0000<1>_MUXF57)
     MUXF6:I0->O           1   0.316   0.000  XLXI_6/Mmux__n0004__n0004<0>__n0004<0>_rn_1 (XLXI_6/_n0004<3>)
     FDC:D                     0.709          XLXI_6/qout_3
    ----------------------------------------
    Total                      8.523ns (3.483ns logic, 5.040ns route)
                                       (40.9% logic, 59.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_17/carry:Q'
  Clock period: 7.811ns (frequency: 128.025MHz)
  Total number of paths / destination ports: 91 / 12
-------------------------------------------------------------------------
Delay:               7.811ns (Levels of Logic = 3)
  Source:            XLXI_2/tem2_1 (FF)
  Destination:       XLXI_2/tem2_3 (FF)
  Source Clock:      XLXI_17/carry:Q rising
  Destination Clock: XLXI_17/carry:Q rising

  Data Path: XLXI_2/tem2_1 to XLXI_2/tem2_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             6   1.085   1.665  XLXI_2/tem2_1 (XLXI_2/tem2_1)
     LUT4:I0->O            3   0.549   1.332  XLXI_2/_n001022 (CHOICE90)
     LUT4:I3->O            1   0.549   0.000  XLXI_2/_n0016_G (N223)
     MUXF5:I1->O           4   0.305   1.440  XLXI_2/_n0016 (XLXI_2/_n0016)
     FDCE:CE                   0.886          XLXI_2/tem2_1
    ----------------------------------------
    Total                      7.811ns (3.374ns logic, 4.437ns route)
                                       (43.2% logic, 56.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_16/carry:Q'
  Clock period: 6.804ns (frequency: 146.972MHz)
  Total number of paths / destination ports: 109 / 14
-------------------------------------------------------------------------
Delay:               6.804ns (Levels of Logic = 2)
  Source:            XLXI_17/tem1_1 (FF)
  Destination:       XLXI_17/carry (FF)
  Source Clock:      XLXI_16/carry:Q rising
  Destination Clock: XLXI_16/carry:Q rising

  Data Path: XLXI_17/tem1_1 to XLXI_17/carry
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            6   1.085   1.665  XLXI_17/tem1_1 (XLXI_17/tem1_1)
     LUT4:I0->O            1   0.549   1.035  XLXI_17/_n00051 (XLXI_17/N2)
     LUT2:I1->O            1   0.549   1.035  XLXI_17/_n00052 (XLXI_17/_n0005)
     FDE:CE                    0.886          XLXI_17/carry
    ----------------------------------------
    Total                      6.804ns (3.069ns logic, 3.735ns route)
                                       (45.1% logic, 54.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_3/qout:Q'
  Clock period: 6.804ns (frequency: 146.972MHz)
  Total number of paths / destination ports: 109 / 14
-------------------------------------------------------------------------
Delay:               6.804ns (Levels of Logic = 2)
  Source:            XLXI_16/tem1_1 (FF)
  Destination:       XLXI_16/carry (FF)
  Source Clock:      XLXI_3/qout:Q rising
  Destination Clock: XLXI_3/qout:Q rising

  Data Path: XLXI_16/tem1_1 to XLXI_16/carry
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            6   1.085   1.665  XLXI_16/tem1_1 (XLXI_16/tem1_1)
     LUT4:I0->O            1   0.549   1.035  XLXI_16/_n00051 (XLXI_16/N2)
     LUT2:I1->O            1   0.549   1.035  XLXI_16/_n00052 (XLXI_16/_n0005)
     FDE:CE                    0.886          XLXI_16/carry
    ----------------------------------------
    Total                      6.804ns (3.069ns logic, 3.735ns route)
                                       (45.1% logic, 54.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 12.225ns (frequency: 81.800MHz)
  Total number of paths / destination ports: 2078 / 43
-------------------------------------------------------------------------
Delay:               12.225ns (Levels of Logic = 16)
  Source:            XLXI_3/cnt_0 (FF)
  Destination:       XLXI_3/qout (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_3/cnt_0 to XLXI_3/qout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   1.085   1.332  XLXI_3/cnt_0 (XLXI_3/cnt_0)
     LUT4:I0->O            1   0.549   1.035  XLXI_3/_n000485 (CHOICE148)
     LUT4_D:I0->LO         1   0.549   0.100  XLXI_3/_n000499 (N230)
     LUT4:I3->O           11   0.549   2.070  XLXI_3/_n0004115_1 (XLXI_3/_n0004115)
     LUT3_L:I2->LO         1   0.549   0.000  XLXI_3/norlut (XLXI_3/N4)
     MUXCY:S->O            1   0.659   0.000  XLXI_3/norcy (XLXI_3/nor_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3/Andcy (XLXI_3/And_cyo)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3/norcy_rn_0 (XLXI_3/nor_cyo1)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3/Andcy_rn_0 (XLXI_3/And_cyo1)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3/norcy_rn_1 (XLXI_3/nor_cyo2)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3/Andcy_rn_1 (XLXI_3/And_cyo2)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3/norcy_rn_2 (XLXI_3/nor_cyo3)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3/Andcy_rn_2 (XLXI_3/And_cyo3)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3/norcy_rn_3 (XLXI_3/nor_cyo4)
     MUXCY:CI->O           1   0.042   0.000  XLXI_3/Andcy_rn_3 (XLXI_3/And_cyo4)
     MUXCY:CI->O           1   0.042   1.035  XLXI_3/norcy_rn_4 (XLXI_3/_n0005)
     INV:I->O              1   0.549   1.035  XLXI_3/_n00021_INV_0 (XLXI_3/_n0002)
     FDE:D                     0.709          XLXI_3/qout
    ----------------------------------------
    Total                     12.225ns (5.618ns logic, 6.607ns route)
                                       (46.0% logic, 54.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_16/carry:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.396ns (Levels of Logic = 3)
  Source:            rst (PAD)
  Destination:       XLXI_17/carry (FF)
  Destination Clock: XLXI_16/carry:Q rising

  Data Path: rst to XLXI_17/carry
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.776   1.566  rst_IBUF (rst_IBUF)
     LUT4:I2->O            1   0.549   1.035  XLXI_17/_n00051 (XLXI_17/N2)
     LUT2:I1->O            1   0.549   1.035  XLXI_17/_n00052 (XLXI_17/_n0005)
     FDE:CE                    0.886          XLXI_17/carry
    ----------------------------------------
    Total                      6.396ns (2.760ns logic, 3.636ns route)
                                       (43.2% logic, 56.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'XLXI_3/qout:Q'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              6.396ns (Levels of Logic = 3)
  Source:            rst (PAD)
  Destination:       XLXI_16/carry (FF)
  Destination Clock: XLXI_3/qout:Q rising

  Data Path: rst to XLXI_16/carry
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.776   1.566  rst_IBUF (rst_IBUF)
     LUT4:I2->O            1   0.549   1.035  XLXI_16/_n00051 (XLXI_16/N2)
     LUT2:I1->O            1   0.549   1.035  XLXI_16/_n00052 (XLXI_16/_n0005)
     FDE:CE                    0.886          XLXI_16/carry
    ----------------------------------------
    Total                      6.396ns (2.760ns logic, 3.636ns route)
                                       (43.2% logic, 56.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              3.228ns (Levels of Logic = 1)
  Source:            rst (PAD)
  Destination:       XLXI_1/qout (FF)
  Destination Clock: clk rising

  Data Path: rst to XLXI_1/qout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.776   1.566  rst_IBUF (rst_IBUF)
     FDE:CE                    0.886          XLXI_3/qout
    ----------------------------------------
    Total                      3.228ns (1.662ns logic, 1.566ns route)
                                       (51.5% logic, 48.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_1/qout:Q'
  Total number of paths / destination ports: 36 / 15
-------------------------------------------------------------------------
Offset:              9.092ns (Levels of Logic = 2)
  Source:            XLXI_6/qout_0 (FF)
  Destination:       dataout<7> (PAD)
  Source Clock:      XLXI_1/qout:Q rising

  Data Path: XLXI_6/qout_0 to dataout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   1.085   1.755  XLXI_6/qout_0 (XLXI_6/qout_0)
     LUT4:I0->O            1   0.549   1.035  XLXI_4/Mrom_qout_inst_lut4_71 (dataout_7_OBUF)
     OBUF:I->O                 4.668          dataout_7_OBUF (dataout<7>)
    ----------------------------------------
    Total                      9.092ns (6.302ns logic, 2.790ns route)
                                       (69.3% logic, 30.7% route)

=========================================================================
CPU : 8.82 / 9.49 s | Elapsed : 9.00 / 10.00 s
 
--> 

Total memory usage is 76804 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   19 (   0 filtered)
Number of infos    :    1 (   0 filtered)