buzzer.rpt

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

FTCPE_clk_div10: FTCPE port map (clk_div1(0),'1',clk,NOT rst,'0');

FTCPE_clk_div11: FTCPE port map (clk_div1(1),clk_div1(3).EXP,clk,NOT rst,'0');

FTCPE_clk_div12: FTCPE port map (clk_div1(2),clk_div1_T(2),clk,NOT rst,'0');
clk_div1_T(2) <= (clk_div1(0) AND clk_div1(1));

FTCPE_clk_div13: FTCPE port map (clk_div1(3),clk_div1_T(3),clk,NOT rst,'0');
clk_div1_T(3) <= ((clk_div2(12).EXP)
	OR (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3)));

FTCPE_clk_div20: FTCPE port map (clk_div2(0),clk_div2_T(0),clk,NOT rst,'0',clk_div2_CE(0));
clk_div2_T(0) <= ((clk_div2(2).EXP)
	OR (state_FFd1 AND state_FFd2 AND NOT state_FFd3 AND 
	NOT clk_div2(0) AND clk_div2(10) AND NOT clk_div2(11) AND NOT clk_div2(1) AND 
	NOT clk_div2(2) AND clk_div2(3) AND NOT clk_div2(4) AND clk_div2(5) AND 
	clk_div2(6) AND clk_div2(7) AND clk_div2(8) AND clk_div2(9) AND 
	NOT clk_div2(12)));
clk_div2_CE(0) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FDCPE_clk_div21: FDCPE port map (clk_div2(1),clk_div2_D(1),clk,NOT rst,'0',clk_div2_CE(1));
clk_div2_D(1) <= ((EXP15_.EXP)
	OR (NOT state_FFd1 AND state_FFd2 AND state_FFd3 AND 
	clk_div2(0) AND NOT clk_div2(10) AND clk_div2(11) AND NOT clk_div2(2) AND 
	NOT clk_div2(3) AND clk_div2(4) AND clk_div2(5) AND NOT clk_div2(6) AND 
	NOT clk_div2(7) AND clk_div2(8) AND clk_div2(9) AND NOT clk_div2(12)));
clk_div2_CE(1) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_clk_div22: FTCPE port map (clk_div2(2),clk_div1(1).EXP,clk,NOT rst,'0',clk_div2_CE(2));
clk_div2_CE(2) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FDCPE_clk_div23: FDCPE port map (clk_div2(3),clk_div2_D(3),clk,NOT rst,'0',clk_div2_CE(3));
clk_div2_D(3) <= ((EXP18_.EXP)
	OR (EXP19_.EXP)
	OR (state_FFd1 AND state_FFd2 AND state_FFd3 AND 
	clk_div2(10) AND NOT clk_div2(11) AND NOT clk_div2(3) AND clk_div2(4) AND 
	clk_div2(5) AND clk_div2(6) AND NOT clk_div2(7) AND clk_div2(8) AND 
	clk_div2(9) AND NOT clk_div2(12))
	OR (NOT state_FFd1 AND NOT state_FFd2 AND state_FFd3 AND 
	clk_div2(0) AND clk_div2(10) AND clk_div2(11) AND clk_div2(2) AND 
	clk_div2(3) AND NOT clk_div2(4) AND NOT clk_div2(5) AND clk_div2(6) AND 
	NOT clk_div2(7) AND clk_div2(8) AND NOT clk_div2(9) AND NOT clk_div2(12)));
clk_div2_CE(3) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_clk_div24: FTCPE port map (clk_div2(4),clk_div2_T(4),clk,NOT rst,'0',clk_div2_CE(4));
clk_div2_T(4) <= ((clk_div2(0).EXP)
	OR (cnt(0).EXP)
	OR (clk_div2(0) AND clk_div2(1) AND clk_div2(2) AND 
	clk_div2(3))
	OR (state_FFd1 AND state_FFd2 AND state_FFd3 AND 
	clk_div2(0) AND clk_div2(10) AND NOT clk_div2(11) AND clk_div2(1) AND 
	clk_div2(2) AND clk_div2(4) AND clk_div2(5) AND clk_div2(6) AND 
	NOT clk_div2(7) AND clk_div2(8) AND clk_div2(9) AND NOT clk_div2(12)));
clk_div2_CE(4) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_clk_div25: FTCPE port map (clk_div2(5),clk_div2_T(5),clk,NOT rst,'0',clk_div2_CE(5));
clk_div2_T(5) <= ((EXP14_.EXP)
	OR (clk_div2(0) AND clk_div2(1) AND clk_div2(2) AND 
	clk_div2(3) AND clk_div2(4)));
clk_div2_CE(5) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_clk_div26: FTCPE port map (clk_div2(6),clk_div2_T(6),clk,NOT rst,'0',clk_div2_CE(6));
clk_div2_T(6) <= ((clk_div2(11).EXP)
	OR (EXP17_.EXP)
	OR (clk_div2(0) AND clk_div2(1) AND clk_div2(2) AND 
	clk_div2(3) AND clk_div2(4) AND clk_div2(5))
	OR (state_FFd1 AND state_FFd2 AND state_FFd3 AND 
	clk_div2(0) AND clk_div2(10) AND NOT clk_div2(11) AND clk_div2(1) AND 
	clk_div2(2) AND clk_div2(4) AND clk_div2(5) AND clk_div2(6) AND 
	NOT clk_div2(7) AND clk_div2(8) AND clk_div2(9) AND NOT clk_div2(12)));
clk_div2_CE(6) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_clk_div27: FTCPE port map (clk_div2(7),clk_div2_T(7),clk,NOT rst,'0',clk_div2_CE(7));
clk_div2_T(7) <= ((EXP20_.EXP)
	OR (clk_div2(0) AND clk_div2(1) AND clk_div2(2) AND 
	clk_div2(3) AND clk_div2(4) AND clk_div2(5) AND clk_div2(6))
	OR (state_FFd1 AND NOT state_FFd2 AND NOT state_FFd3 AND 
	clk_div2(0) AND NOT clk_div2(10) AND clk_div2(11) AND clk_div2(1) AND 
	clk_div2(2) AND clk_div2(4) AND clk_div2(5) AND clk_div2(6) AND 
	clk_div2(7) AND clk_div2(8) AND NOT clk_div2(9) AND NOT clk_div2(12)));
clk_div2_CE(7) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_clk_div28: FTCPE port map (clk_div2(8),clk_div2_T(8),clk,NOT rst,'0',clk_div2_CE(8));
clk_div2_T(8) <= ((EXP13_.EXP)
	OR (clk_div2(0) AND clk_div2(1) AND clk_div2(2) AND 
	clk_div2(3) AND clk_div2(4) AND clk_div2(5) AND clk_div2(6) AND 
	clk_div2(7)));
clk_div2_CE(8) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_clk_div29: FTCPE port map (clk_div2(9),clk_div2_T(9),clk,NOT rst,'0',clk_div2_CE(9));
clk_div2_T(9) <= ((EXP10_.EXP)
	OR (clk_div2(0) AND clk_div2(1) AND clk_div2(2) AND 
	clk_div2(3) AND clk_div2(4) AND clk_div2(5) AND clk_div2(6) AND 
	clk_div2(7) AND clk_div2(8))
	OR (state_FFd1 AND state_FFd2 AND state_FFd3 AND 
	clk_div2(0) AND clk_div2(10) AND NOT clk_div2(11) AND clk_div2(1) AND 
	clk_div2(2) AND NOT clk_div2(3) AND clk_div2(4) AND clk_div2(5) AND 
	clk_div2(6) AND NOT clk_div2(7) AND clk_div2(8) AND clk_div2(9) AND 
	NOT clk_div2(12)));
clk_div2_CE(9) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_clk_div210: FTCPE port map (clk_div2(10),clk_div2_T(10),clk,NOT rst,'0',clk_div2_CE(10));
clk_div2_T(10) <= ((clk_div1(0).EXP)
	OR (clk_div2(0) AND clk_div2(1) AND clk_div2(2) AND 
	clk_div2(3) AND clk_div2(4) AND clk_div2(5) AND clk_div2(6) AND 
	clk_div2(7) AND clk_div2(8) AND clk_div2(9))
	OR (state_FFd1 AND state_FFd2 AND state_FFd3 AND 
	clk_div2(0) AND clk_div2(10) AND NOT clk_div2(11) AND clk_div2(1) AND 
	clk_div2(2) AND NOT clk_div2(3) AND clk_div2(4) AND clk_div2(5) AND 
	clk_div2(6) AND NOT clk_div2(7) AND clk_div2(8) AND clk_div2(9) AND 
	NOT clk_div2(12)));
clk_div2_CE(10) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_clk_div211: FTCPE port map (clk_div2(11),clk_div2_T(11),clk,NOT rst,'0',clk_div2_CE(11));
clk_div2_T(11) <= ((EXP16_.EXP)
	OR (clk_div2(0) AND clk_div2(10) AND clk_div2(1) AND 
	clk_div2(2) AND clk_div2(3) AND clk_div2(4) AND clk_div2(5) AND 
	clk_div2(6) AND clk_div2(7) AND clk_div2(8) AND clk_div2(9)));
clk_div2_CE(11) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_clk_div212: FTCPE port map (clk_div2(12),clk_div2_T(12),clk,NOT rst,'0',clk_div2_CE(12));
clk_div2_T(12) <= (clk_div2(0) AND clk_div2(10) AND clk_div2(11) AND 
	clk_div2(1) AND clk_div2(2) AND clk_div2(3) AND clk_div2(4) AND 
	clk_div2(5) AND clk_div2(6) AND clk_div2(7) AND clk_div2(8) AND 
	clk_div2(9));
clk_div2_CE(12) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt0: FTCPE port map (cnt(0),'1',clk,NOT rst,'0',cnt_CE(0));
cnt_CE(0) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt1: FTCPE port map (cnt(1),cnt(0),clk,NOT rst,'0',cnt_CE(1));
cnt_CE(1) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt2: FTCPE port map (cnt(2),cnt_T(2),clk,NOT rst,'0',cnt_CE(2));
cnt_T(2) <= (cnt(0) AND cnt(1));
cnt_CE(2) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt3: FTCPE port map (cnt(3),cnt_T(3),clk,NOT rst,'0',cnt_CE(3));
cnt_T(3) <= (cnt(0) AND cnt(1) AND cnt(2));
cnt_CE(3) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt4: FTCPE port map (cnt(4),cnt_T(4),clk,NOT rst,'0',cnt_CE(4));
cnt_T(4) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3));
cnt_CE(4) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt5: FTCPE port map (cnt(5),cnt_T(5),clk,NOT rst,'0',cnt_CE(5));
cnt_T(5) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4));
cnt_CE(5) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt6: FTCPE port map (cnt(6),cnt_T(6),clk,NOT rst,'0',cnt_CE(6));
cnt_T(6) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND 
	cnt(5));
cnt_CE(6) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt7: FTCPE port map (cnt(7),cnt_T(7),clk,NOT rst,'0',cnt_CE(7));
cnt_T(7) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND 
	cnt(5) AND cnt(6));
cnt_CE(7) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt8: FTCPE port map (cnt(8),cnt_T(8),clk,NOT rst,'0',cnt_CE(8));
cnt_T(8) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND 
	cnt(5) AND cnt(6) AND cnt(7));
cnt_CE(8) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt9: FTCPE port map (cnt(9),cnt_T(9),clk,NOT rst,'0',cnt_CE(9));
cnt_T(9) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND 
	cnt(5) AND cnt(6) AND cnt(7) AND cnt(8));
cnt_CE(9) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt10: FTCPE port map (cnt(10),cnt_T(10),clk,NOT rst,'0',cnt_CE(10));
cnt_T(10) <= (cnt(0) AND cnt(1) AND cnt(2) AND cnt(3) AND cnt(4) AND 
	cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
cnt_CE(10) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt11: FTCPE port map (cnt(11),cnt_T(11),clk,NOT rst,'0',cnt_CE(11));
cnt_T(11) <= (cnt(0) AND cnt(10) AND cnt(1) AND cnt(2) AND cnt(3) AND 
	cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND cnt(9));
cnt_CE(11) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt12: FTCPE port map (cnt(12),cnt_T(12),clk,NOT rst,'0',cnt_CE(12));
cnt_T(12) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(1) AND cnt(2) AND 
	cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND cnt(8) AND 
	cnt(9));
cnt_CE(12) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));

FTCPE_cnt13: FTCPE port map (cnt(13),cnt_T(13),clk,NOT rst,'0',cnt_CE(13));
cnt_T(13) <= (cnt(0) AND cnt(10) AND cnt(11) AND cnt(12) AND cnt(1) AND 
	cnt(2) AND cnt(3) AND cnt(4) AND cnt(5) AND cnt(6) AND cnt(7) AND 
	cnt(8) AND cnt(9));
cnt_CE(13) <= (clk_div1(0) AND NOT clk_div1(1) AND NOT clk_div1(2) AND 
	clk_div1(3));