buzzer.mfd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

   cnt<6>.AR = !rst;
   cnt<6>.CE = clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;

MACROCELL | 0 | 5 | cnt<7>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 17 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 4 | 0 | 3 | 0 | 6
INPUTS | 13 | cnt<0>  | cnt<1>  | cnt<2>  | cnt<3>  | cnt<4>  | cnt<5>  | cnt<6>  | clk  | rst  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>
INPUTMC | 11 | 1 | 15 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 1 | 4 | 1 | 3 | 1 | 17 | 1 | 11 | 1 | 2 | 1 | 10
INPUTP | 2 | 143 | 79
EQ | 6 | 
   cnt<7>.T = cnt<0> & cnt<1> & cnt<2> & cnt<3> & cnt<4> & 
	cnt<5> & cnt<6>;
   cnt<7>.CLK = clk;
   cnt<7>.AR = !rst;
   cnt<7>.CE = clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;

MACROCELL | 0 | 4 | cnt<8>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 16 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 3 | 0 | 6
INPUTS | 14 | cnt<0>  | cnt<1>  | cnt<2>  | cnt<3>  | cnt<4>  | cnt<5>  | cnt<6>  | cnt<7>  | clk  | rst  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>
INPUTMC | 12 | 1 | 15 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 1 | 4 | 1 | 3 | 0 | 5 | 1 | 17 | 1 | 11 | 1 | 2 | 1 | 10
INPUTP | 2 | 143 | 79
EQ | 6 | 
   cnt<8>.T = cnt<0> & cnt<1> & cnt<2> & cnt<3> & cnt<4> & 
	cnt<5> & cnt<6> & cnt<7>;
   cnt<8>.CLK = clk;
   cnt<8>.AR = !rst;
   cnt<8>.CE = clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;

MACROCELL | 0 | 3 | cnt<9>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 0 | 8 | 0 | 7 | 0 | 6
INPUTS | 15 | cnt<0>  | cnt<1>  | cnt<2>  | cnt<3>  | cnt<4>  | cnt<5>  | cnt<6>  | cnt<7>  | cnt<8>  | clk  | rst  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>
INPUTMC | 13 | 1 | 15 | 1 | 8 | 1 | 7 | 1 | 6 | 1 | 5 | 1 | 4 | 1 | 3 | 0 | 5 | 0 | 4 | 1 | 17 | 1 | 11 | 1 | 2 | 1 | 10
INPUTP | 2 | 143 | 79
EQ | 6 | 
   cnt<9>.T = cnt<0> & cnt<1> & cnt<2> & cnt<3> & cnt<4> & 
	cnt<5> & cnt<6> & cnt<7> & cnt<8>;
   cnt<9>.CLK = clk;
   cnt<9>.AR = !rst;
   cnt<9>.CE = clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;

MACROCELL | 0 | 6 | cnt<21>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 3 | 0 | 2 | 0 | 1 | 0 | 0
INPUTS | 27 | cnt<0>  | cnt<10>  | cnt<11>  | cnt<12>  | cnt<13>  | cnt<14>  | cnt<15>  | cnt<16>  | cnt<17>  | cnt<18>  | cnt<19>  | cnt<1>  | cnt<20>  | cnt<2>  | cnt<3>  | cnt<4>  | cnt<5>  | cnt<6>  | cnt<7>  | cnt<8>  | cnt<9>  | clk  | rst  | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>
INPUTMC | 25 | 1 | 15 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 0 | 8 | 1 | 8 | 0 | 7 | 1 | 7 | 1 | 6 | 1 | 5 | 1 | 4 | 1 | 3 | 0 | 5 | 0 | 4 | 0 | 3 | 1 | 17 | 1 | 11 | 1 | 2 | 1 | 10
INPUTP | 2 | 143 | 79
EQ | 8 | 
   cnt<21>.T = cnt<0> & cnt<10> & cnt<11> & cnt<12> & cnt<13> & 
	cnt<14> & cnt<15> & cnt<16> & cnt<17> & cnt<18> & 
	cnt<19> & cnt<1> & cnt<20> & cnt<2> & cnt<3> & cnt<4> & 
	cnt<5> & cnt<6> & cnt<7> & cnt<8> & cnt<9>;
   cnt<21>.CLK = clk;
   cnt<21>.AR = !rst;
   cnt<21>.CE = clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>;

MACROCELL | 1 | 17 | clk_div1<0>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 41 | 6 | 2 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 13 | 1 | 16 | 6 | 10 | 6 | 8 | 1 | 12 | 6 | 14 | 1 | 14 | 6 | 6 | 6 | 11 | 6 | 16 | 6 | 4 | 1 | 0 | 1 | 9 | 1 | 15 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 0 | 8 | 1 | 8 | 0 | 7 | 1 | 7 | 1 | 6 | 1 | 5 | 1 | 4 | 1 | 3 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 6 | 1 | 10 | 1 | 2
INPUTS | 18 | clk  | rst  | state_FFd1  | state_FFd2  | state_FFd3  | clk_div2<0>  | clk_div2<10>  | clk_div2<11>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>
INPUTMC | 16 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 13 | 1 | 16 | 6 | 10 | 6 | 8 | 1 | 12 | 6 | 14 | 1 | 14 | 6 | 6 | 6 | 11 | 6 | 16 | 6 | 4 | 1 | 0 | 1 | 9
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 1 | 16
EQ | 18 | 
   clk_div1<0>.T = Vcc;
   clk_div1<0>.CLK = clk;
   clk_div1<0>.AR = !rst;
    clk_div1<0>.EXP  =  state_FFd1 & state_FFd2 & !state_FFd3 & 
	!clk_div2<0> & clk_div2<10> & !clk_div2<11> & !clk_div2<1> & 
	!clk_div2<2> & clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12>
	# !state_FFd1 & !state_FFd2 & state_FFd3 & 
	clk_div2<0> & clk_div2<10> & clk_div2<11> & !clk_div2<1> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & !clk_div2<5> & 
	clk_div2<6> & !clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12>
	# !state_FFd1 & !state_FFd2 & !state_FFd3 & 
	!clk_div2<0> & clk_div2<10> & clk_div2<11> & clk_div2<1> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & !clk_div2<8> & clk_div2<9> & 
	!clk_div2<12>

MACROCELL | 1 | 11 | clk_div1<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 41 | 6 | 2 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 13 | 1 | 16 | 6 | 10 | 6 | 8 | 1 | 12 | 6 | 14 | 1 | 14 | 6 | 6 | 6 | 11 | 6 | 16 | 6 | 4 | 1 | 0 | 1 | 9 | 1 | 15 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 0 | 8 | 1 | 8 | 0 | 7 | 1 | 7 | 1 | 6 | 1 | 5 | 1 | 4 | 1 | 3 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 6 | 1 | 10 | 1 | 2
INPUTS | 19 | clk_div2<0>  | clk_div2<1>  | state_FFd1  | state_FFd2  | clk  | rst  | state_FFd3  | clk_div2<10>  | clk_div2<11>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | clk_div1<3>.EXP
INPUTMC | 17 | 1 | 13 | 6 | 8 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 16 | 6 | 10 | 1 | 12 | 6 | 14 | 1 | 14 | 6 | 6 | 6 | 11 | 6 | 16 | 6 | 4 | 1 | 0 | 1 | 9 | 1 | 10
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 1 | 12
IMPORTS | 1 | 1 | 10
EQ | 14 | 
   !clk_div1<1>.T = ;Imported pterms FB2_11
	  !clk_div1<0>
	# !clk_div1<1> & !clk_div1<2> & clk_div1<3>;
   clk_div1<1>.CLK = clk;
   clk_div1<1>.AR = !rst;
    clk_div1<1>.EXP  =  clk_div2<0> & clk_div2<1>
	# !state_FFd1 & !state_FFd2 & state_FFd3 & 
	clk_div2<0> & clk_div2<10> & clk_div2<11> & clk_div2<2> & 
	clk_div2<3> & !clk_div2<4> & !clk_div2<5> & clk_div2<6> & 
	!clk_div2<7> & clk_div2<8> & !clk_div2<9> & !clk_div2<12>
	# !state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div2<10> & clk_div2<11> & clk_div2<1> & clk_div2<2> & 
	clk_div2<3> & !clk_div2<4> & clk_div2<5> & clk_div2<6> & 
	clk_div2<7> & !clk_div2<8> & clk_div2<9> & !clk_div2<12>

MACROCELL | 1 | 2 | clk_div1<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 40 | 6 | 2 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 13 | 1 | 16 | 6 | 10 | 6 | 8 | 1 | 12 | 6 | 14 | 1 | 14 | 6 | 6 | 6 | 11 | 6 | 16 | 6 | 4 | 1 | 0 | 1 | 9 | 1 | 15 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 0 | 8 | 1 | 8 | 0 | 7 | 1 | 7 | 1 | 6 | 1 | 5 | 1 | 4 | 1 | 3 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 6 | 1 | 10
INPUTS | 4 | clk_div1<0>  | clk_div1<1>  | clk  | rst
INPUTMC | 2 | 1 | 17 | 1 | 11
INPUTP | 2 | 143 | 79
EQ | 3 | 
   clk_div1<2>.T = clk_div1<0> & clk_div1<1>;
   clk_div1<2>.CLK = clk;
   clk_div1<2>.AR = !rst;

MACROCELL | 1 | 10 | clk_div1<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 41 | 6 | 2 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 13 | 1 | 16 | 6 | 10 | 6 | 8 | 1 | 12 | 6 | 14 | 1 | 14 | 6 | 6 | 6 | 11 | 6 | 16 | 6 | 4 | 1 | 0 | 1 | 9 | 1 | 15 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 9 | 0 | 8 | 1 | 8 | 0 | 7 | 1 | 7 | 1 | 6 | 1 | 5 | 1 | 4 | 1 | 3 | 0 | 5 | 0 | 4 | 0 | 3 | 0 | 6 | 1 | 10 | 1 | 11
INPUTS | 7 | clk_div1<0>  | clk_div1<1>  | clk_div1<2>  | clk_div1<3>  | clk  | rst  | clk_div2<12>.EXP
INPUTMC | 5 | 1 | 17 | 1 | 11 | 1 | 2 | 1 | 10 | 1 | 9
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 1 | 11
IMPORTS | 1 | 1 | 9
EQ | 8 | 
   clk_div1<3>.T = clk_div1<0> & !clk_div1<1> & !clk_div1<2> & 
	clk_div1<3>
;Imported pterms FB2_10
	# clk_div1<0> & clk_div1<1> & clk_div1<2>;
   clk_div1<3>.CLK = clk;
   clk_div1<3>.AR = !rst;
    clk_div1<3>.EXP  =  !clk_div1<0>
	# !clk_div1<1> & !clk_div1<2> & clk_div1<3>

MACROCELL | 1 | 1 | EXP10_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 1 | 0
INPUTS | 16 | state_FFd1  | state_FFd2  | state_FFd3  | clk_div2<0>  | clk_div2<10>  | clk_div2<11>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>
INPUTMC | 16 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 13 | 1 | 16 | 6 | 10 | 6 | 8 | 1 | 12 | 6 | 14 | 1 | 14 | 6 | 6 | 6 | 11 | 6 | 16 | 6 | 4 | 1 | 0 | 1 | 9
EXPORTS | 1 | 1 | 0
EQ | 20 | 
       EXP10_.EXP  =  state_FFd1 & state_FFd2 & !state_FFd3 & 
	!clk_div2<0> & clk_div2<10> & !clk_div2<11> & !clk_div2<1> & 
	!clk_div2<2> & clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12>
	# !state_FFd1 & state_FFd2 & state_FFd3 & 
	clk_div2<0> & !clk_div2<10> & clk_div2<11> & !clk_div2<1> & 
	!clk_div2<2> & !clk_div2<3> & clk_div2<4> & clk_div2<5> & 
	!clk_div2<6> & !clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12>
	# !state_FFd1 & state_FFd2 & !state_FFd3 & 
	!clk_div2<0> & !clk_div2<10> & clk_div2<11> & clk_div2<1> & 
	!clk_div2<2> & clk_div2<3> & clk_div2<4> & !clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12>
	# !state_FFd1 & !state_FFd2 & !state_FFd3 & 
	!clk_div2<0> & clk_div2<10> & clk_div2<11> & clk_div2<1> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & !clk_div2<8> & clk_div2<9> & 
	!clk_div2<12>

MACROCELL | 6 | 0 | EXP11_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 6 | 1
INPUTS | 16 | state_FFd1  | state_FFd2  | state_FFd3  | clk_div2<0>  | clk_div2<10>  | clk_div2<11>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>
INPUTMC | 16 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 13 | 1 | 16 | 6 | 10 | 6 | 8 | 1 | 12 | 6 | 14 | 1 | 14 | 6 | 6 | 6 | 11 | 6 | 16 | 6 | 4 | 1 | 0 | 1 | 9
EXPORTS | 1 | 6 | 1
EQ | 10 | 
       EXP11_.EXP  =  state_FFd1 & !state_FFd2 & !state_FFd3 & 
	clk_div2<0> & !clk_div2<10> & clk_div2<11> & clk_div2<1> & 
	clk_div2<2> & !clk_div2<3> & clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12>
	# !state_FFd1 & !state_FFd2 & !state_FFd3 & 
	!clk_div2<0> & clk_div2<10> & clk_div2<11> & clk_div2<1> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & !clk_div2<8> & clk_div2<9> & 
	!clk_div2<12>

MACROCELL | 6 | 1 | EXP12_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 6 | 2
INPUTS | 17 | state_FFd1  | state_FFd2  | state_FFd3  | clk_div2<0>  | clk_div2<10>  | clk_div2<11>  | clk_div2<1>  | clk_div2<2>  | clk_div2<3>  | clk_div2<4>  | clk_div2<5>  | clk_div2<6>  | clk_div2<7>  | clk_div2<8>  | clk_div2<9>  | clk_div2<12>  | EXP11_.EXP
INPUTMC | 17 | 0 | 2 | 0 | 1 | 0 | 0 | 1 | 13 | 1 | 16 | 6 | 10 | 6 | 8 | 1 | 12 | 6 | 14 | 1 | 14 | 6 | 6 | 6 | 11 | 6 | 16 | 6 | 4 | 1 | 0 | 1 | 9 | 6 | 0
EXPORTS | 1 | 6 | 2
IMPORTS | 1 | 6 | 0
EQ | 36 | 
       EXP12_.EXP  =  state_FFd1 & state_FFd2 & !state_FFd3 & 
	!clk_div2<0> & clk_div2<10> & !clk_div2<11> & !clk_div2<1> & 
	!clk_div2<2> & clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12>
	# state_FFd1 & !state_FFd2 & state_FFd3 & 
	clk_div2<0> & !clk_div2<10> & clk_div2<11> & !clk_div2<1> & 
	!clk_div2<2> & !clk_div2<3> & !clk_div2<4> & clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & !clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12>
	# !state_FFd1 & state_FFd2 & state_FFd3 & 
	clk_div2<0> & !clk_div2<10> & clk_div2<11> & !clk_div2<1> & 
	!clk_div2<2> & !clk_div2<3> & clk_div2<4> & clk_div2<5> & 
	!clk_div2<6> & !clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12>
	# !state_FFd1 & state_FFd2 & !state_FFd3 & 
	!clk_div2<0> & !clk_div2<10> & clk_div2<11> & clk_div2<1> & 
	!clk_div2<2> & clk_div2<3> & clk_div2<4> & !clk_div2<5> & 
	clk_div2<6> & clk_div2<7> & clk_div2<8> & clk_div2<9> & 
	!clk_div2<12>
	# !state_FFd1 & !state_FFd2 & state_FFd3 & 
	clk_div2<0> & clk_div2<10> & clk_div2<11> & !clk_div2<1> & 
	clk_div2<2> & clk_div2<3> & !clk_div2<4> & !clk_div2<5> & 
	clk_div2<6> & !clk_div2<7> & clk_div2<8> & !clk_div2<9> & 
	!clk_div2<12>
;Imported pterms FB7_1
	# state_FFd1 & !state_FFd2 & !state_FFd3