📄 ledwater.rpt
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cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: ledwater Date: 2-21-2006, 11:41AM
Device Used: XC95144XL-10-TQ144
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
35 /144 ( 24%) 116 /720 ( 16%) 67 /432 ( 15%) 35 /144 ( 24%) 14 /117 ( 12%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 18/18* 24/54 54/90 0/15
FB2 5/18 6/54 14/90 0/15
FB3 12/18 37/54 48/90 12/15
FB4 0/18 0/54 0/90 0/15
FB5 0/18 0/54 0/90 0/14
FB6 0/18 0/54 0/90 0/13
FB7 0/18 0/54 0/90 0/15
FB8 0/18 0/54 0/90 0/15
----- ----- ----- -----
35/144 67/432 116/720 12/117
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 2 2 | I/O : 14 109
Output : 12 12 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 14 14
** Power Data **
There are 35 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************* Summary of Mapped Logic ************************
** 12 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
dataout<10> 4 26 FB3_1 39 I/O O STD FAST RESET
dataout<9> 4 26 FB3_3 41 I/O O STD FAST RESET
dataout<8> 4 26 FB3_4 44 I/O O STD FAST RESET
dataout<5> 4 26 FB3_5 33 I/O O STD FAST RESET
dataout<11> 4 26 FB3_6 34 I/O O STD FAST RESET
dataout<4> 4 26 FB3_9 40 I/O O STD FAST RESET
dataout<7> 4 26 FB3_10 48 I/O O STD FAST RESET
dataout<3> 4 26 FB3_11 43 I/O O STD FAST RESET
dataout<2> 4 26 FB3_12 45 I/O O STD FAST RESET
dataout<1> 4 26 FB3_14 49 I/O O STD FAST RESET
dataout<6> 4 26 FB3_15 50 I/O O STD FAST RESET
dataout<0> 4 26 FB3_17 51 I/O O STD FAST RESET
** 23 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
cnt<9> 3 11 FB1_1 STD RESET
cnt<8> 3 10 FB1_2 STD RESET
cnt<7> 3 9 FB1_3 STD RESET
cnt<6> 3 8 FB1_4 STD RESET
cnt<5> 3 7 FB1_5 STD RESET
cnt<22> 3 24 FB1_6 STD RESET
cnt<21> 3 23 FB1_7 STD RESET
cnt<20> 3 22 FB1_8 STD RESET
cnt<19> 3 21 FB1_9 STD RESET
cnt<18> 3 20 FB1_10 STD RESET
cnt<17> 3 19 FB1_11 STD RESET
cnt<16> 3 18 FB1_12 STD RESET
cnt<15> 3 17 FB1_13 STD RESET
cnt<14> 3 16 FB1_14 STD RESET
cnt<13> 3 15 FB1_15 STD RESET
cnt<12> 3 14 FB1_16 STD RESET
cnt<11> 3 13 FB1_17 STD RESET
cnt<10> 3 12 FB1_18 STD RESET
cnt<0> 2 2 FB2_14 STD RESET
cnt<4> 3 6 FB2_15 STD RESET
cnt<3> 3 5 FB2_16 STD RESET
cnt<2> 3 4 FB2_17 STD RESET
cnt<1> 3 3 FB2_18 STD RESET
** 2 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
clk FB4_5 128 I/O I
rst FB7_2 71 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 24/30
Number of signals used by logic mapping into function block: 24
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
cnt<9> 3 0 0 2 FB1_1 23 I/O (b)
cnt<8> 3 0 0 2 FB1_2 16 I/O (b)
cnt<7> 3 0 0 2 FB1_3 17 I/O (b)
cnt<6> 3 0 0 2 FB1_4 25 I/O (b)
cnt<5> 3 0 0 2 FB1_5 19 I/O (b)
cnt<22> 3 0 0 2 FB1_6 20 I/O (b)
cnt<21> 3 0 0 2 FB1_7 (b) (b)
cnt<20> 3 0 0 2 FB1_8 21 I/O (b)
cnt<19> 3 0 0 2 FB1_9 22 I/O (b)
cnt<18> 3 0 0 2 FB1_10 31 I/O (b)
cnt<17> 3 0 0 2 FB1_11 24 I/O (b)
cnt<16> 3 0 0 2 FB1_12 26 I/O (b)
cnt<15> 3 0 0 2 FB1_13 (b) (b)
cnt<14> 3 0 0 2 FB1_14 27 I/O (b)
cnt<13> 3 0 0 2 FB1_15 28 I/O (b)
cnt<12> 3 0 0 2 FB1_16 35 I/O (b)
cnt<11> 3 0 0 2 FB1_17 30 GCK/I/O (b)
cnt<10> 3 0 0 2 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 9: cnt<16> 17: cnt<3>
2: cnt<0> 10: cnt<17> 18: cnt<4>
3: cnt<10> 11: cnt<18> 19: cnt<5>
4: cnt<11> 12: cnt<19> 20: cnt<6>
5: cnt<12> 13: cnt<1> 21: cnt<7>
6: cnt<13> 14: cnt<20> 22: cnt<8>
7: cnt<14> 15: cnt<21> 23: cnt<9>
8: cnt<15> 16: cnt<2> 24: rst
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
cnt<9> XX..........X..XXXXXXX.X................ 11
cnt<8> XX..........X..XXXXXX..X................ 10
cnt<7> XX..........X..XXXXX...X................ 9
cnt<6> XX..........X..XXXX....X................ 8
cnt<5> XX..........X..XXX.....X................ 7
cnt<22> XXXXXXXXXXXXXXXXXXXXXXXX................ 24
cnt<21> XXXXXXXXXXXXXX.XXXXXXXXX................ 23
cnt<20> XXXXXXXXXXXXX..XXXXXXXXX................ 22
cnt<19> XXXXXXXXXXX.X..XXXXXXXXX................ 21
cnt<18> XXXXXXXXXX..X..XXXXXXXXX................ 20
cnt<17> XXXXXXXXX...X..XXXXXXXXX................ 19
cnt<16> XXXXXXXX....X..XXXXXXXXX................ 18
cnt<15> XXXXXXX.....X..XXXXXXXXX................ 17
cnt<14> XXXXXX......X..XXXXXXXXX................ 16
cnt<13> XXXXX.......X..XXXXXXXXX................ 15
cnt<12> XXXX........X..XXXXXXXXX................ 14
cnt<11> XXX.........X..XXXXXXXXX................ 13
cnt<10> XX..........X..XXXXXXXXX................ 12
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 6/48
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 142 I/O
(unused) 0 0 0 5 FB2_2 143 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 4 I/O
(unused) 0 0 0 5 FB2_5 2 GTS/I/O
(unused) 0 0 0 5 FB2_6 3 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 7 I/O
(unused) 0 0 0 5 FB2_11 9 I/O
(unused) 0 0 0 5 FB2_12 10 I/O
(unused) 0 0 0 5 FB2_13 12 I/O
cnt<0> 2 0 0 3 FB2_14 11 I/O (b)
cnt<4> 3 0 0 2 FB2_15 13 I/O (b)
cnt<3> 3 0 0 2 FB2_16 14 I/O (b)
cnt<2> 3 0 0 2 FB2_17 15 I/O (b)
cnt<1> 3 0 0 2 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: clk 3: cnt<1> 5: cnt<3>
2: cnt<0> 4: cnt<2> 6: rst
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
cnt<0> X....X.................................. 2
cnt<4> XXXXXX.................................. 6
cnt<3> XXXX.X.................................. 5
cnt<2> XXX..X.................................. 4
cnt<1> XX...X.................................. 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 37/17
Number of signals used by logic mapping into function block: 37
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
dataout<10> 4 0 0 1 FB3_1 39 I/O O
(unused) 0 0 0 5 FB3_2 32 GCK/I/O
dataout<9> 4 0 0 1 FB3_3 41 I/O O
dataout<8> 4 0 0 1 FB3_4 44 I/O O
dataout<5> 4 0 0 1 FB3_5 33 I/O O
dataout<11> 4 0 0 1 FB3_6 34 I/O O
(unused) 0 0 0 5 FB3_7 46 I/O
(unused) 0 0 0 5 FB3_8 38 GCK/I/O
dataout<4> 4 0 0 1 FB3_9 40 I/O O
dataout<7> 4 0 0 1 FB3_10 48 I/O O
dataout<3> 4 0 0 1 FB3_11 43 I/O O
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