ledwater.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: ledwater.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "ledwater.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "ledwater"
Output Format                      : NGC
Target Device                      : xc2s50-5-TQ144

---- Source Options
Top Module Name                    : ledwater
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : ledwater.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/SPARTAN2/vhdl/Interface/waterlight/ledwater.vhd" in Library work.
Architecture arch of Entity ledwater is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ledwater> (Architecture <arch>).
Entity <ledwater> analyzed. Unit <ledwater> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ledwater>.
    Related source file is "E:/temp/SPARTAN2/vhdl/Interface/waterlight/ledwater.vhd".
    Found 16x12-bit ROM for signal <dataout>.
    Found 28-bit up counter for signal <cnt>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
Unit <ledwater> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x12-bit ROM                     : 1
# Counters                         : 1
 28-bit up counter                 : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ledwater> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ledwater, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ledwater.ngr
Top Level Output File Name         : ledwater
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 14

Macro Statistics :
# ROMs                             : 1
#      16x12-bit ROM               : 1
# Registers                        : 1
#      28-bit register             : 1
# Adders/Subtractors               : 1
#      28-bit adder                : 1

Cell Usage :
# BELS                             : 97
#      GND                         : 1
#      INV                         : 2
#      LUT1_L                      : 27
#      LUT4                        : 12
#      MUXCY                       : 27
#      VCC                         : 1
#      XORCY                       : 27
# FlipFlops/Latches                : 28
#      FDC                         : 28
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 13
#      IBUF                        : 1
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                      21  out of    768     2%  
 Number of Slice Flip Flops:            28  out of   1536     1%  
 Number of 4 input LUTs:                39  out of   1536     2%  
 Number of bonded IOBs:                 14  out of     96    14%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 28    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.582ns (Maximum Frequency: 151.929MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 11.152ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 6.582ns (frequency: 151.929MHz)
  Total number of paths / destination ports: 406 / 28
-------------------------------------------------------------------------
Delay:               6.582ns (Levels of Logic = 5)
  Source:            cnt_24 (FF)
  Destination:       cnt_27 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_24 to cnt_27
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   1.292   2.500  cnt_24 (cnt_24)
     LUT1_L:I0->LO         1   0.653   0.000  cnt_24_rt (cnt_24_rt)
     MUXCY:S->O            1   0.784   0.000  ledwater_cnt__n0000<24>cy (ledwater_cnt__n0000<24>_cyo)
     MUXCY:CI->O           1   0.050   0.000  ledwater_cnt__n0000<25>cy (ledwater_cnt__n0000<25>_cyo)
     MUXCY:CI->O           0   0.050   0.000  ledwater_cnt__n0000<26>cy (ledwater_cnt__n0000<26>_cyo)
     XORCY:CI->O           1   0.500   0.000  ledwater_cnt__n0000<27>_xor (cnt__n0000<27>)
     FDC:D                     0.753          cnt_27
    ----------------------------------------
    Total                      6.582ns (4.082ns logic, 2.500ns route)
                                       (62.0% logic, 38.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 48 / 12
-------------------------------------------------------------------------
Offset:              11.152ns (Levels of Logic = 2)
  Source:            cnt_25 (FF)
  Destination:       dataout<11> (PAD)
  Source Clock:      clk rising

  Data Path: cnt_25 to dataout<11>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   1.292   2.500  cnt_25 (cnt_25)
     LUT4:I3->O            1   0.653   1.150  Mrom_dataout_inst_lut4_21 (dataout_2_OBUF)
     OBUF:I->O                 5.557          dataout_2_OBUF (dataout<2>)
    ----------------------------------------
    Total                     11.152ns (7.502ns logic, 3.650ns route)
                                       (67.3% logic, 32.7% route)

=========================================================================
CPU : 4.05 / 4.47 s | Elapsed : 4.00 / 5.00 s
 
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Total memory usage is 75780 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)