vga.twr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

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Release 7.1.04i Trace H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise e:\temp\spartan2\vhdl\interface\vga\vga.ise
-intstyle ise -e 3 -l 3 -s 6 -xml vga vga.ncd -o vga.twr vga.pcf


Design file:              vga.ncd
Physical constraint file: vga.pcf
Device,speed:             xc2s50,-6 (PRODUCTION 1.27 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
orient      |    5.187(F)|   -3.423(F)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
b           |   11.299(F)|clk_BUFGP         |   0.000|
g           |   13.745(F)|clk_BUFGP         |   0.000|
r           |   11.335(F)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    3.195|         |         |    4.225|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
orient         |b              |   11.789|
orient         |g              |   11.870|
orient         |r              |   11.408|
---------------+---------------+---------+

Analysis completed Fri Feb 24 13:21:28 2006
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Peak Memory Usage: 63 MB