vga.vm6

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_IBUF | 3372 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | NULL | clk_IBUF | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | clk_int<1> | 3373 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | clk_int<1>.Q | clk_int<1> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | clk_int<1>.SI | clk_int<1> | 0 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_int<0> | 3377 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | clk_int<0>.Q | clk_int<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_IBUF | 3372 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | NULL | clk_IBUF | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | clk_int<1>.D1 | 3487 | ? | 0 | 0 | clk_int<1> | NULL | NULL | clk_int<1>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | clk_int<1>.D2 | 3488 | ? | 0 | 4096 | clk_int<1> | NULL | NULL | clk_int<1>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | clk_int<0>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | clk_int<1>.CLKF | 3489 | ? | 0 | 4096 | clk_int<1> | NULL | NULL | clk_int<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_IBUF

SRFF_INSTANCE | clk_int<1>.REG | clk_int<1> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | clk_int<1>.D | 3486 | ? | 0 | 0 | clk_int<1> | NULL | NULL | clk_int<1>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | clk_int<1>.CLKF | 3489 | ? | 0 | 4096 | clk_int<1> | NULL | NULL | clk_int<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_IBUF
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | clk_int<1>.Q | 3490 | ? | 0 | 0 | clk_int<1> | NULL | NULL | clk_int<1>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | ll<0> | vga_COPY_0_COPY_0 | 2155877376 | 1 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<4> | 3356 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<4>.Q | cc<4> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | ll<0> | 3374 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<0>.Q | ll<0> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | ll<0>.SI | ll<0> | 0 | 1 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<4> | 3356 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<4>.Q | cc<4> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | ll<0>.D1 | 3492 | ? | 0 | 4096 | ll<0> | NULL | NULL | ll<0>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | ll<0>.D2 | 3493 | ? | 0 | 4096 | ll<0> | NULL | NULL | ll<0>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 0 | IV_DC
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | ll<0>.CLKF | 3494 | ? | 0 | 4096 | ll<0> | NULL | NULL | ll<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_FALSE | cc<4>

SRFF_INSTANCE | ll<0>.REG | ll<0> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | ll<0>.D | 3491 | ? | 0 | 0 | ll<0> | NULL | NULL | ll<0>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | ll<0>.CLKF | 3494 | ? | 0 | 4096 | ll<0> | NULL | NULL | ll<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_FALSE | cc<4>
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | ll<0>.Q | 3495 | ? | 0 | 0 | ll<0> | NULL | NULL | ll<0>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | fs<0> | vga_COPY_0_COPY_0 | 2155877376 | 1 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_int<1> | 3373 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | clk_int<1>.Q | clk_int<1> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | fs<0> | 3375 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<0>.Q | fs<0> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | fs<0>.SI | fs<0> | 0 | 1 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_int<1> | 3373 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | clk_int<1>.Q | clk_int<1> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | fs<0>.D1 | 3497 | ? | 0 | 4096 | fs<0> | NULL | NULL | fs<0>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | fs<0>.D2 | 3498 | ? | 0 | 4096 | fs<0> | NULL | NULL | fs<0>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 0 | IV_DC
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | fs<0>.CLKF | 3499 | ? | 0 | 4096 | fs<0> | NULL | NULL | fs<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_int<1>

SRFF_INSTANCE | fs<0>.REG | fs<0> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | fs<0>.D | 3496 | ? | 0 | 0 | fs<0> | NULL | NULL | fs<0>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | fs<0>.CLKF | 3499 | ? | 0 | 4096 | fs<0> | NULL | NULL | fs<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_int<1>
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | fs<0>.Q | 3500 | ? | 0 | 0 | fs<0> | NULL | NULL | fs<0>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | Inv+PrldLow+Tff+OptxMapped | ll<1> | vga_COPY_0_COPY_0 | 2155877632 | 10 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<0> | 3374 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<0>.Q | ll<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<5> | 3358 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<5>.Q | ll<5> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<6> | 3359 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<6>.Q | ll<6> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<7> | 3360 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<7>.Q | ll<7> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<4> | 3363 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<4>.Q | ll<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<8> | 3364 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<8>.Q | ll<8> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<3> | 3366 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<3>.Q | ll<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<2> | 3370 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<2>.Q | ll<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<1> | 3376 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<1>.Q | ll<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<4> | 3356 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<4>.Q | cc<4> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | ll<1> | 3376 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<1>.Q | ll<1> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | ll<1>.SI | ll<1> | 0 | 10 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<0> | 3374 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<0>.Q | ll<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<5> | 3358 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<5>.Q | ll<5> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<6> | 3359 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<6>.Q | ll<6> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<7> | 3360 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<7>.Q | ll<7> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<4> | 3363 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<4>.Q | ll<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<8> | 3364 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<8>.Q | ll<8> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<3> | 3366 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<3>.Q | ll<3> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<2> | 3370 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<2>.Q | ll<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<1> | 3376 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<1>.Q | ll<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<4> | 3356 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<4>.Q | cc<4> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | ll<1>.D1 | 3502 | ? | 0 | 4096 | ll<1> | NULL | NULL | ll<1>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | ll<1>.D2 | 3503 | ? | 0 | 4096 | ll<1> | NULL | NULL | ll<1>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_FALSE | ll<0>
SPPTERM | 8 | IV_TRUE | ll<5> | IV_TRUE | ll<6> | IV_TRUE | ll<7> | IV_FALSE | ll<4> | IV_TRUE | ll<8> | IV_FALSE | ll<3> | IV_FALSE | ll<2> | IV_FALSE | ll<1>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | ll<1>.CLKF | 3504 | ? | 0 | 4096 | ll<1> | NULL | NULL | ll<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_FALSE | cc<4>

SRFF_INSTANCE | ll<1>.REG | ll<1> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | ll<1>.D | 3501 | ? | 0 | 0 | ll<1> | NULL | NULL | ll<1>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | ll<1>.CLKF | 3504 | ? | 0 | 4096 | ll<1> | NULL | NULL | ll<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_FALSE | cc<4>
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | ll<1>.Q | 3505 | ? | 0 | 0 | ll<1> | NULL | NULL | ll<1>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | clk_int<0> | vga_COPY_0_COPY_0 | 2155877376 | 1 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_IBUF | 3372 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | NULL | clk_IBUF | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | clk_int<0> | 3377 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | clk_int<0>.Q | clk_int<0> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | clk_int<0>.SI | clk_int<0> | 0 | 1 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_IBUF | 3372 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | NULL | clk_IBUF | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | clk_int<0>.D1 | 3507 | ? | 0 | 4096 | clk_int<0> | NULL | NULL | clk_int<0>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | clk_int<0>.D2 | 3508 | ? | 0 | 4096 | clk_int<0> | NULL | NULL | clk_int<0>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 0 | IV_DC
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | clk_int<0>.CLKF | 3509 | ? | 0 | 4096 | clk_int<0> | NULL | NULL | clk_int<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_IBUF

SRFF_INSTANCE | clk_int<0>.REG | clk_int<0> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | clk_int<0>.D | 3506 | ? | 0 | 0 | clk_int<0> | NULL | NULL | clk_int<0>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | clk_int<0>.CLKF | 3509 | ? | 0 | 4096 | clk_int<0> | NULL | NULL | clk_int<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_IBUF
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | clk_int<0>.Q | 3510 | ? | 0 | 0 | clk_int<0> | NULL | NULL | clk_int<0>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | fs<1> | vga_COPY_0_COPY_0 | 2155877376 | 2 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | fs<0> | 3375 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<0>.Q | fs<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_int<1> | 3373 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | clk_int<1>.Q | clk_int<1> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | fs<1> | 3378 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<1>.Q | fs<1> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | fs<1>.SI | fs<1> | 0 | 2 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | fs<0> | 3375 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<0>.Q | fs<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_int<1> | 3373 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | clk_int<1>.Q | clk_int<1> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | fs<1>.D1 | 3512 | ? | 0 | 0 | fs<1> | NULL | NULL | fs<1>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | fs<1>.D2 | 3513 | ? | 0 | 4096 | fs<1> | NULL | NULL | fs<1>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 1 | IV_TRUE | fs<0>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | fs<1>.CLKF | 3514 | ? | 0 | 4096 | fs<1> | NULL | NULL | fs<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_int<1>

SRFF_INSTANCE | fs<1>.REG | fs<1> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | fs<1>.D | 3511 | ? | 0 | 0 | fs<1> | NULL | NULL | fs<1>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | fs<1>.CLKF | 3514 | ? | 0 | 4096 | fs<1> | NULL | NULL | fs<1>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_int<1>
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | fs<1>.Q | 3515 | ? | 0 | 0 | fs<1> | NULL | NULL | fs<1>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | Inv+OptxMapped | hs_OBUF | vga_COPY_0_COPY_0 | 2155872512 | 2 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<4> | 3356 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<4>.Q | cc<4> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 |