vga.vm6

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | ll<3> | 3366 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<3>.Q | ll<3> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | ll<3>.SI | ll<3> | 0 | 4 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<2> | 3370 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<2>.Q | ll<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<0> | 3374 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<0>.Q | ll<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<1> | 3376 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<1>.Q | ll<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<4> | 3356 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<4>.Q | cc<4> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | ll<3>.D1 | 3457 | ? | 0 | 4096 | ll<3> | NULL | NULL | ll<3>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | ll<3>.D2 | 3458 | ? | 0 | 4096 | ll<3> | NULL | NULL | ll<3>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 3 | IV_TRUE | ll<2> | IV_TRUE | ll<0> | IV_TRUE | ll<1>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | ll<3>.CLKF | 3459 | ? | 0 | 4096 | ll<3> | NULL | NULL | ll<3>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_FALSE | cc<4>

SRFF_INSTANCE | ll<3>.REG | ll<3> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | ll<3>.D | 3456 | ? | 0 | 0 | ll<3> | NULL | NULL | ll<3>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | ll<3>.CLKF | 3459 | ? | 0 | 4096 | ll<3> | NULL | NULL | ll<3>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_FALSE | cc<4>
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | ll<3>.Q | 3460 | ? | 0 | 0 | ll<3> | NULL | NULL | ll<3>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+OptxMapped | mmd<0> | vga_COPY_0_COPY_0 | 2155873280 | 3 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | mmd<1> | 3362 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | mmd<1>.Q | mmd<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | mmd<0> | 3367 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | mmd<0>.Q | mmd<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | orient_IBUF | 3361 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | NULL | orient_IBUF | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | mmd<0> | 3367 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | mmd<0>.Q | mmd<0> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | mmd<0>.SI | mmd<0> | 0 | 3 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | mmd<1> | 3362 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | mmd<1>.Q | mmd<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | mmd<0> | 3367 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | mmd<0>.Q | mmd<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | orient_IBUF | 3361 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | NULL | orient_IBUF | 0 | 5 | II_IMUX
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | mmd<0>.D1 | 3462 | ? | 0 | 4096 | mmd<0> | NULL | NULL | mmd<0>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | mmd<0>.D2 | 3463 | ? | 0 | 4096 | mmd<0> | NULL | NULL | mmd<0>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 2 | IV_FALSE | mmd<1> | IV_FALSE | mmd<0>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | mmd<0>.CLKF | 3464 | ? | 0 | 4096 | mmd<0> | NULL | NULL | mmd<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_FALSE | orient_IBUF

SRFF_INSTANCE | mmd<0>.REG | mmd<0> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | mmd<0>.D | 3461 | ? | 0 | 0 | mmd<0> | NULL | NULL | mmd<0>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | mmd<0>.CLKF | 3464 | ? | 0 | 4096 | mmd<0> | NULL | NULL | mmd<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_FALSE | orient_IBUF
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | mmd<0>.Q | 3465 | ? | 0 | 0 | mmd<0> | NULL | NULL | mmd<0>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | cc<3> | vga_COPY_0_COPY_0 | 2155877376 | 4 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<2> | 3357 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<2>.Q | cc<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<1> | 3365 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<1>.Q | cc<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<0> | 3369 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<0>.Q | cc<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | fs<2> | 3371 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<2>.Q | fs<2> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | cc<3> | 3368 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<3>.Q | cc<3> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | cc<3>.SI | cc<3> | 0 | 4 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<2> | 3357 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<2>.Q | cc<2> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<1> | 3365 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<1>.Q | cc<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<0> | 3369 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<0>.Q | cc<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | fs<2> | 3371 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<2>.Q | fs<2> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | cc<3>.D1 | 3467 | ? | 0 | 0 | cc<3> | NULL | NULL | cc<3>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | cc<3>.D2 | 3468 | ? | 0 | 4096 | cc<3> | NULL | NULL | cc<3>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 3 | IV_TRUE | cc<2> | IV_TRUE | cc<1> | IV_TRUE | cc<0>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | cc<3>.CLKF | 3469 | ? | 0 | 4096 | cc<3> | NULL | NULL | cc<3>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | fs<2>

SRFF_INSTANCE | cc<3>.REG | cc<3> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | cc<3>.D | 3466 | ? | 0 | 0 | cc<3> | NULL | NULL | cc<3>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | cc<3>.CLKF | 3469 | ? | 0 | 4096 | cc<3> | NULL | NULL | cc<3>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | fs<2>
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | cc<3>.Q | 3470 | ? | 0 | 0 | cc<3> | NULL | NULL | cc<3>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | cc<0> | vga_COPY_0_COPY_0 | 2155877376 | 1 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | fs<2> | 3371 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<2>.Q | fs<2> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | cc<0> | 3369 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<0>.Q | cc<0> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | cc<0>.SI | cc<0> | 0 | 1 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | fs<2> | 3371 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<2>.Q | fs<2> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | cc<0>.D1 | 3472 | ? | 0 | 4096 | cc<0> | NULL | NULL | cc<0>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | cc<0>.D2 | 3473 | ? | 0 | 4096 | cc<0> | NULL | NULL | cc<0>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 0 | IV_DC
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | cc<0>.CLKF | 3474 | ? | 0 | 4096 | cc<0> | NULL | NULL | cc<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | fs<2>

SRFF_INSTANCE | cc<0>.REG | cc<0> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | cc<0>.D | 3471 | ? | 0 | 0 | cc<0> | NULL | NULL | cc<0>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | cc<0>.CLKF | 3474 | ? | 0 | 4096 | cc<0> | NULL | NULL | cc<0>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | fs<2>
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | cc<0>.Q | 3475 | ? | 0 | 0 | cc<0> | NULL | NULL | cc<0>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | ll<2> | vga_COPY_0_COPY_0 | 2155877376 | 3 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<0> | 3374 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<0>.Q | ll<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<1> | 3376 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<1>.Q | ll<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<4> | 3356 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<4>.Q | cc<4> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | ll<2> | 3370 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<2>.Q | ll<2> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | ll<2>.SI | ll<2> | 0 | 3 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<0> | 3374 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<0>.Q | ll<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | ll<1> | 3376 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | ll<1>.Q | ll<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | cc<4> | 3356 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | cc<4>.Q | cc<4> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | ll<2>.D1 | 3477 | ? | 0 | 4096 | ll<2> | NULL | NULL | ll<2>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | ll<2>.D2 | 3478 | ? | 0 | 4096 | ll<2> | NULL | NULL | ll<2>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 2 | IV_TRUE | ll<0> | IV_TRUE | ll<1>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | ll<2>.CLKF | 3479 | ? | 0 | 4096 | ll<2> | NULL | NULL | ll<2>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_FALSE | cc<4>

SRFF_INSTANCE | ll<2>.REG | ll<2> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | ll<2>.D | 3476 | ? | 0 | 0 | ll<2> | NULL | NULL | ll<2>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | ll<2>.CLKF | 3479 | ? | 0 | 4096 | ll<2> | NULL | NULL | ll<2>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_FALSE | cc<4>
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | ll<2>.Q | 3480 | ? | 0 | 0 | ll<2> | NULL | NULL | ll<2>.REG | 0 | 8 | SRFF_Q

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | fs<2> | vga_COPY_0_COPY_0 | 2155877376 | 3 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | fs<0> | 3375 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<0>.Q | fs<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | fs<1> | 3378 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<1>.Q | fs<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_int<1> | 3373 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | clk_int<1>.Q | clk_int<1> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM
NODE | fs<2> | 3371 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<2>.Q | fs<2> | 1 | 0 | MC_UIM

SIGNAL_INSTANCE | fs<2>.SI | fs<2> | 0 | 3 | 3
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | fs<0> | 3375 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<0>.Q | fs<0> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | fs<1> | 3378 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | fs<1>.Q | fs<1> | 1 | 0 | MC_UIM
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_int<1> | 3373 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | clk_int<1>.Q | clk_int<1> | 1 | 0 | MC_UIM
OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1
SIGNAL | NODE | fs<2>.D1 | 3482 | ? | 0 | 0 | fs<2> | NULL | NULL | fs<2>.SI | 1 | 9 | MC_SI_D1
SPPTERM | 0 | IV_ZERO
OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2
SIGNAL | NODE | fs<2>.D2 | 3483 | ? | 0 | 4096 | fs<2> | NULL | NULL | fs<2>.SI | 2 | 9 | MC_SI_D2
SPPTERM | 2 | IV_TRUE | fs<0> | IV_TRUE | fs<1>
OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF
SIGNAL | NODE | fs<2>.CLKF | 3484 | ? | 0 | 4096 | fs<2> | NULL | NULL | fs<2>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_int<1>

SRFF_INSTANCE | fs<2>.REG | fs<2> | 0 | 2 | 1
INPUT_NODE_TYPE | 0 | 8 | SRFF_D
NODE | fs<2>.D | 3481 | ? | 0 | 0 | fs<2> | NULL | NULL | fs<2>.XOR | 0 | 7 | ALU_F
INPUT_NODE_TYPE | 1 | 8 | SRFF_C
SIGNAL | NODE | fs<2>.CLKF | 3484 | ? | 0 | 4096 | fs<2> | NULL | NULL | fs<2>.SI | 3 | 9 | MC_SI_CLKF
SPPTERM | 1 | IV_TRUE | clk_int<1>
OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q
NODE | fs<2>.Q | 3485 | ? | 0 | 0 | fs<2> | NULL | NULL | fs<2>.REG | 0 | 8 | SRFF_Q

INPUT_INSTANCE | 0 | 0 | NULL | clk_IBUF | vga_COPY_0_COPY_0 | 16 | 1 | 1
INPUT_NODE_TYPE | 0 | 5 | II_IN
NODE | clk | 3398 | PI | 0 | 0 | vga_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE
OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX
NODE | clk_IBUF | 3372 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | NULL | clk_IBUF | 0 | 5 | II_IMUX

MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | clk_int<1> | vga_COPY_0_COPY_0 | 2155877376 | 2 | 1
INPUT_NODE_TYPE | 1 | 100 | NOTYPE
NODE | clk_int<0> | 3377 | ? | 0 | 0 | vga_COPY_0_COPY_0 | NULL | clk_int<0>.Q | clk_int<0> | 1 | 0 | MC_UIM