vga.syr

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

 Number of Slice Flip Flops:            21  out of   1536     1%  
 Number of 4 input LUTs:                46  out of   1536     2%  
 Number of bonded IOBs:                  7  out of     96     7%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
fs_2:Q                             | NONE                   | 5     |
clk_int_1:Q                        | NONE                   | 3     |
cc_4:Q                             | NONE                   | 9     |
clk                                | BUFGP                  | 4     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 7.615ns (Maximum Frequency: 131.320MHz)
   Minimum input arrival time before clock: 4.983ns
   Maximum output required time after clock: 17.165ns
   Maximum combinational path delay: 8.594ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'fs_2:Q'
  Clock period: 5.364ns (frequency: 186.428MHz)
  Total number of paths / destination ports: 15 / 5
-------------------------------------------------------------------------
Delay:               5.364ns (Levels of Logic = 2)
  Source:            cc_4 (FF)
  Destination:       cc_4 (FF)
  Source Clock:      fs_2:Q rising
  Destination Clock: fs_2:Q rising

  Data Path: cc_4 to cc_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              18   1.085   2.700  cc_4 (cc_4)
     LUT1_L:I0->LO         0   0.549   0.000  cc_4_rt (cc_4_rt)
     XORCY:LI->O           1   0.321   0.000  vga_cc__n0000<4>_xor (cc__n0000<4>)
     FD:D                      0.709          cc_4
    ----------------------------------------
    Total                      5.364ns (2.664ns logic, 2.700ns route)
                                       (49.7% logic, 50.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_int_1:Q'
  Clock period: 4.008ns (frequency: 249.501MHz)
  Total number of paths / destination ports: 6 / 3
-------------------------------------------------------------------------
Delay:               4.008ns (Levels of Logic = 1)
  Source:            fs_2 (FF)
  Destination:       fs_2 (FF)
  Source Clock:      clk_int_1:Q rising
  Destination Clock: clk_int_1:Q rising

  Data Path: fs_2 to fs_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               6   1.085   1.665  fs_2 (fs_2)
     LUT3:I0->O            1   0.549   0.000  vga_fs__n0000<2>_xor11 (fs__n0000<2>)
     FD:D                      0.709          fs_2
    ----------------------------------------
    Total                      4.008ns (2.343ns logic, 1.665ns route)
                                       (58.5% logic, 41.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'cc_4:Q'
  Clock period: 7.615ns (frequency: 131.320MHz)
  Total number of paths / destination ports: 126 / 18
-------------------------------------------------------------------------
Delay:               7.615ns (Levels of Logic = 2)
  Source:            ll_4 (FF)
  Destination:       ll_7 (FF)
  Source Clock:      cc_4:Q falling
  Destination Clock: cc_4:Q falling

  Data Path: ll_4 to ll_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q            7   1.085   1.755  ll_4 (ll_4)
     LUT3:I2->O            1   0.549   1.035  _n0016_SW0 (N233)
     LUT4:I2->O            9   0.549   1.908  _n0016 (_n0016)
     FDR_1:R                   0.734          ll_0
    ----------------------------------------
    Total                      7.615ns (2.917ns logic, 4.698ns route)
                                       (38.3% logic, 61.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.419ns (frequency: 184.536MHz)
  Total number of paths / destination ports: 10 / 6
-------------------------------------------------------------------------
Delay:               5.419ns (Levels of Logic = 1)
  Source:            mmd_0 (FF)
  Destination:       mmd_1 (FF)
  Source Clock:      clk falling
  Destination Clock: clk falling

  Data Path: mmd_0 to mmd_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE_1:C->Q           8   1.085   1.845  mmd_0 (mmd_0)
     LUT3:I0->O            2   0.549   1.206  _n00171 (_n0017)
     FDRE_1:R                  0.734          mmd_0
    ----------------------------------------
    Total                      5.419ns (2.368ns logic, 3.051ns route)
                                       (43.7% logic, 56.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              4.983ns (Levels of Logic = 2)
  Source:            orient (PAD)
  Destination:       mmd_1 (FF)
  Destination Clock: clk falling

  Data Path: orient to mmd_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.776   1.566  orient_IBUF (orient_IBUF)
     INV:I->O              2   0.549   1.206  mmd_ClkEn_INV1_INV_0 (mmd_0_N0)
     FDRE_1:CE                 0.886          mmd_0
    ----------------------------------------
    Total                      4.983ns (2.211ns logic, 2.772ns route)
                                       (44.4% logic, 55.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'fs_2:Q'
  Total number of paths / destination ports: 30 / 4
-------------------------------------------------------------------------
Offset:              14.789ns (Levels of Logic = 5)
  Source:            cc_4 (FF)
  Destination:       g (PAD)
  Source Clock:      fs_2:Q rising

  Data Path: cc_4 to g
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              18   1.085   2.700  cc_4 (cc_4)
     LUT4:I1->O            1   0.549   1.035  grbp<3>26 (CHOICE857)
     LUT2:I0->O            1   0.549   1.035  grbp<3>28 (CHOICE858)
     LUT4:I3->O            1   0.549   1.035  grbp<3>65 (CHOICE861)
     LUT4:I3->O            1   0.549   1.035  _n00501 (g_OBUF)
     OBUF:I->O                 4.668          g_OBUF (g)
    ----------------------------------------
    Total                     14.789ns (7.949ns logic, 6.840ns route)
                                       (53.7% logic, 46.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 9 / 3
-------------------------------------------------------------------------
Offset:              13.934ns (Levels of Logic = 5)
  Source:            mmd_0 (FF)
  Destination:       g (PAD)
  Source Clock:      clk falling

  Data Path: mmd_0 to g
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE_1:C->Q           8   1.085   1.845  mmd_0 (mmd_0)
     LUT4:I3->O            1   0.549   1.035  grbp<3>26 (CHOICE857)
     LUT2:I0->O            1   0.549   1.035  grbp<3>28 (CHOICE858)
     LUT4:I3->O            1   0.549   1.035  grbp<3>65 (CHOICE861)
     LUT4:I3->O            1   0.549   1.035  _n00501 (g_OBUF)
     OBUF:I->O                 4.668          g_OBUF (g)
    ----------------------------------------
    Total                     13.934ns (7.949ns logic, 5.985ns route)
                                       (57.0% logic, 43.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cc_4:Q'
  Total number of paths / destination ports: 47 / 4
-------------------------------------------------------------------------
Offset:              17.165ns (Levels of Logic = 7)
  Source:            ll_8 (FF)
  Destination:       b (PAD)
  Source Clock:      cc_4:Q falling

  Data Path: ll_8 to b
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR_1:C->Q            9   1.085   1.908  ll_8 (ll_8)
     LUT2:I1->O            1   0.549   1.035  grby<1>81 (CHOICE902)
     LUT4:I2->O            1   0.549   1.035  grby<1>89 (CHOICE903)
     LUT4:I1->O            1   0.549   1.035  grby<1>108 (CHOICE905)
     LUT4:I1->O            1   0.549   1.035  grby<1>137 (grby<1>)
     LUT4:I1->O            1   0.549   1.035  Ker01 (N01)
     LUT3:I0->O            1   0.549   1.035  _n00481 (b_OBUF)
     OBUF:I->O                 4.668          b_OBUF (b)
    ----------------------------------------
    Total                     17.165ns (9.047ns logic, 8.118ns route)
                                       (52.7% logic, 47.3% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Delay:               8.594ns (Levels of Logic = 3)
  Source:            orient (PAD)
  Destination:       b (PAD)

  Data Path: orient to b
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   0.776   1.566  orient_IBUF (orient_IBUF)
     LUT3:I1->O            1   0.549   1.035  _n00491 (r_OBUF)
     OBUF:I->O                 4.668          r_OBUF (r)
    ----------------------------------------
    Total                      8.594ns (5.993ns logic, 2.601ns route)
                                       (69.7% logic, 30.3% route)

=========================================================================
CPU : 6.15 / 6.56 s | Elapsed : 6.00 / 6.00 s
 
--> 

Total memory usage is 76804 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    3 (   0 filtered)
Number of infos    :    1 (   0 filtered)