i2c.mfd

Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档

	# inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd2
;Imported pterms FB6_6
	# !inner_state_FFd1 & !inner_state_FFd3 & 
	!inner_state_FFd2
	# !inner_state_FFd1 & !main_state_FFd1 & 
	!i2c_state_FFd3 & !inner_state_FFd2 & i2c_state_FFd2
;Imported pterms FB6_8
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	!main_state_FFd1 & !inner_state_FFd3 & !i2c_state_FFd2
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	!inner_state_FFd3 & !i2c_state_FFd2 & !i2c_state_FFd1
	# !inner_state_FFd1 & !main_state_FFd2 & 
	i2c_state_FFd3 & !inner_state_FFd2 & i2c_state_FFd2 & 
	!i2c_state_FFd1
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	!main_state_FFd2 & !inner_state_FFd3 & !i2c_state_FFd3 & 
	!i2c_state_FFd1;
   inner_state_FFd2.CLK = clk;
   inner_state_FFd2.AR = !rst;

MACROCELL | 7 | 4 | i2c_state_FFd2
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 33 | 6 | 6 | 6 | 15 | 5 | 12 | 0 | 16 | 0 | 15 | 5 | 15 | 7 | 3 | 5 | 5 | 7 | 4 | 7 | 2 | 6 | 3 | 2 | 2 | 2 | 0 | 2 | 8 | 2 | 7 | 5 | 0 | 7 | 13 | 0 | 17 | 5 | 7 | 5 | 13 | 5 | 14 | 5 | 16 | 6 | 0 | 6 | 1 | 6 | 2 | 6 | 4 | 6 | 5 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 14 | 6 | 17 | 7 | 14
INPUTS | 12 | main_state_FFd1  | main_state_FFd2  | i2c_state_FFd2  | i2c_state_FFd1  | phase3  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | i2c_state_FFd3  | clk  | rst  | i2c_state_FFd3.EXP
INPUTMC | 10 | 0 | 16 | 0 | 15 | 7 | 4 | 7 | 2 | 1 | 0 | 6 | 16 | 5 | 12 | 5 | 15 | 7 | 3 | 7 | 3
INPUTP | 2 | 143 | 79
IMPORTS | 1 | 7 | 3
EQ | 13 | 
   i2c_state_FFd2.T = main_state_FFd1 & !i2c_state_FFd2 & 
	i2c_state_FFd1
	# !main_state_FFd1 & !main_state_FFd2 & 
	i2c_state_FFd2
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	main_state_FFd1 & !inner_state_FFd3 & i2c_state_FFd3 & 
	!i2c_state_FFd2
;Imported pterms FB8_4
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	main_state_FFd2 & !inner_state_FFd3 & i2c_state_FFd3 & 
	!i2c_state_FFd2;
   i2c_state_FFd2.CLK = clk;
   i2c_state_FFd2.AR = !rst;

MACROCELL | 7 | 2 | i2c_state_FFd1
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 32 | 6 | 6 | 7 | 14 | 5 | 2 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 0 | 7 | 5 | 6 | 11 | 5 | 11 | 0 | 16 | 5 | 15 | 0 | 17 | 7 | 4 | 7 | 2 | 6 | 3 | 2 | 2 | 2 | 8 | 6 | 17 | 5 | 7 | 5 | 13 | 5 | 14 | 5 | 16 | 6 | 0 | 6 | 1 | 6 | 2 | 6 | 5 | 6 | 8 | 6 | 9 | 6 | 10 | 7 | 3
INPUTS | 11 | main_state_FFd1  | main_state_FFd2  | i2c_state_FFd1  | phase3  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | i2c_state_FFd3  | i2c_state_FFd2  | clk  | rst
INPUTMC | 9 | 0 | 16 | 0 | 15 | 7 | 2 | 1 | 0 | 6 | 16 | 5 | 12 | 5 | 15 | 7 | 3 | 7 | 4
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 7 | 3
EQ | 10 | 
   i2c_state_FFd1.T = !main_state_FFd1 & !main_state_FFd2 & 
	i2c_state_FFd1
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	main_state_FFd1 & !inner_state_FFd3 & !i2c_state_FFd3 & 
	i2c_state_FFd2 & !i2c_state_FFd1;
   i2c_state_FFd1.CLK = clk;
   i2c_state_FFd1.AR = !rst;
    i2c_state_FFd1.EXP  =  phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	main_state_FFd1 & !main_state_FFd2 & !inner_state_FFd3 & 
	!i2c_state_FFd2

MACROCELL | 6 | 3 | link
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 7 | 6 | 7 | 6 | 4 | 6 | 3 | 2 | 6 | 6 | 0 | 6 | 1 | 6 | 2
INPUTS | 14 | phase1  | inner_state_FFd1  | main_state_FFd1  | inner_state_FFd3  | inner_state_FFd2  | i2c_state_FFd2  | link  | i2c_state_FFd3  | i2c_state_FFd1  | main_state_FFd2  | EXP21_.EXP  | EXP22_.EXP  | clk  | rst
INPUTMC | 12 | 1 | 2 | 5 | 12 | 0 | 16 | 5 | 15 | 5 | 6 | 7 | 4 | 6 | 3 | 7 | 3 | 7 | 2 | 0 | 15 | 6 | 2 | 6 | 4
INPUTP | 2 | 143 | 79
IMPORTS | 2 | 6 | 2 | 6 | 4
EQ | 52 | 
   !link.D = !main_state_FFd2 & i2c_state_FFd3 & 
	i2c_state_FFd2 & !i2c_state_FFd1 & !link
	# phase1 & inner_state_FFd1 & !main_state_FFd1 & 
	!inner_state_FFd3 & inner_state_FFd2 & i2c_state_FFd2 & !link
	# inner_state_FFd1 & !inner_state_FFd3 & 
	!i2c_state_FFd3 & inner_state_FFd2 & i2c_state_FFd2 & 
	!i2c_state_FFd1 & !link
;Imported pterms FB7_3
	# !inner_state_FFd4 & !i2c_state_FFd3 & 
	i2c_state_FFd2 & i2c_state_FFd1 & !link
	# !inner_state_FFd1 & !main_state_FFd2 & 
	i2c_state_FFd3 & i2c_state_FFd2 & !link
	# !main_state_FFd2 & inner_state_FFd3 & 
	i2c_state_FFd3 & i2c_state_FFd2 & !link
	# inner_state_FFd3 & !i2c_state_FFd3 & 
	i2c_state_FFd2 & i2c_state_FFd1 & !link
	# phase1 & inner_state_FFd1 & !inner_state_FFd3 & 
	inner_state_FFd2 & i2c_state_FFd2 & !i2c_state_FFd1 & !link
;Imported pterms FB7_2
	# !phase1 & !inner_state_FFd4 & !inner_state_FFd3 & 
	!inner_state_FFd2 & !link
	# inner_state_FFd4 & inner_state_FFd1 & 
	inner_state_FFd3 & inner_state_FFd2 & !link
	# !inner_state_FFd4 & inner_state_FFd1 & 
	!inner_state_FFd3 & inner_state_FFd2 & !link
	# !inner_state_FFd4 & !inner_state_FFd3 & 
	i2c_state_FFd3 & !inner_state_FFd2 & !link
	# !inner_state_FFd1 & !i2c_state_FFd3 & 
	i2c_state_FFd2 & i2c_state_FFd1 & !link
;Imported pterms FB7_5
	# !main_state_FFd1 & !main_state_FFd2
	# !phase3 & inner_state_FFd4 & !link
	# !phase3 & inner_state_FFd3 & !link
	# !phase3 & inner_state_FFd2 & !link
	# !main_state_FFd1 & !i2c_state_FFd3 & 
	i2c_state_FFd2 & !link
;Imported pterms FB7_6
	# phase3 & !inner_state_FFd4 & inner_state_FFd1 & 
	!main_state_FFd1 & !inner_state_FFd3 & i2c_state_FFd3
	# phase3 & !inner_state_FFd4 & inner_state_FFd1 & 
	!main_state_FFd1 & !inner_state_FFd3 & inner_state_FFd2 & 
	!i2c_state_FFd2
	# phase3 & !inner_state_FFd4 & inner_state_FFd1 & 
	!inner_state_FFd3 & i2c_state_FFd3 & !i2c_state_FFd2 & !i2c_state_FFd1
	# phase3 & !inner_state_FFd4 & inner_state_FFd1 & 
	!inner_state_FFd3 & inner_state_FFd2 & !i2c_state_FFd2 & 
	!i2c_state_FFd1
	# phase3 & inner_state_FFd1 & !main_state_FFd2 & 
	!inner_state_FFd3 & !i2c_state_FFd3 & inner_state_FFd2 & 
	i2c_state_FFd2 & !i2c_state_FFd1;
   link.CLK = clk;
   link.AR = !rst;

MACROCELL | 2 | 4 | clk_div<0>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 11 | 1 | 0 | 1 | 2 | 1 | 3 | 1 | 1 | 1 | 9 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTS | 2 | clk  | rst
INPUTP | 2 | 143 | 79
EQ | 3 | 
   clk_div<0>.T = Vcc;
   clk_div<0>.CLK = clk;
   clk_div<0>.AR = !rst;

MACROCELL | 1 | 9 | clk_div<1>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 10 | 1 | 0 | 1 | 2 | 1 | 3 | 1 | 1 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTS | 3 | clk_div<0>  | clk  | rst
INPUTMC | 1 | 2 | 4
INPUTP | 2 | 143 | 79
EQ | 3 | 
   clk_div<1>.T = clk_div<0>;
   clk_div<1>.CLK = clk;
   clk_div<1>.AR = !rst;

MACROCELL | 1 | 17 | clk_div<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 10 | 1 | 0 | 1 | 2 | 1 | 3 | 1 | 1 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTS | 10 | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk_div<7>  | clk  | rst
INPUTMC | 8 | 2 | 4 | 1 | 9 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTP | 2 | 143 | 79
EQ | 6 | 
   !clk_div<2>.T = !clk_div<0>
	# !clk_div<1>
	# !clk_div<2> & !clk_div<3> & !clk_div<4> & 
	clk_div<5> & clk_div<6> & !clk_div<7>;
   clk_div<2>.CLK = clk;
   clk_div<2>.AR = !rst;

MACROCELL | 1 | 8 | clk_div<3>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 9 | 1 | 0 | 1 | 2 | 1 | 3 | 1 | 1 | 1 | 17 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTS | 5 | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk  | rst
INPUTMC | 3 | 2 | 4 | 1 | 9 | 1 | 17
INPUTP | 2 | 143 | 79
EQ | 3 | 
   clk_div<3>.T = clk_div<0> & clk_div<1> & clk_div<2>;
   clk_div<3>.CLK = clk;
   clk_div<3>.AR = !rst;

MACROCELL | 1 | 7 | clk_div<4>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 8 | 1 | 0 | 1 | 2 | 1 | 3 | 1 | 1 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 6
INPUTS | 6 | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk  | rst
INPUTMC | 4 | 2 | 4 | 1 | 9 | 1 | 17 | 1 | 8
INPUTP | 2 | 143 | 79
EQ | 4 | 
   clk_div<4>.T = clk_div<0> & clk_div<1> & clk_div<2> & 
	clk_div<3>;
   clk_div<4>.CLK = clk;
   clk_div<4>.AR = !rst;

MACROCELL | 1 | 16 | clk_div<5>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 8 | 1 | 0 | 1 | 2 | 1 | 3 | 1 | 1 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 6
INPUTS | 10 | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk_div<7>  | clk  | rst
INPUTMC | 8 | 2 | 4 | 1 | 9 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTP | 2 | 143 | 79
EQ | 7 | 
   clk_div<5>.T = clk_div<0> & clk_div<1> & clk_div<2> & 
	clk_div<3> & clk_div<4>
	# clk_div<0> & clk_div<1> & !clk_div<2> & 
	!clk_div<3> & !clk_div<4> & clk_div<5> & clk_div<6> & 
	!clk_div<7>;
   clk_div<5>.CLK = clk;
   clk_div<5>.AR = !rst;

MACROCELL | 1 | 15 | clk_div<6>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 8 | 1 | 0 | 1 | 2 | 1 | 3 | 1 | 1 | 1 | 17 | 1 | 16 | 1 | 15 | 1 | 6
INPUTS | 10 | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk_div<7>  | clk  | rst
INPUTMC | 8 | 2 | 4 | 1 | 9 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTP | 2 | 143 | 79
EQ | 7 | 
   clk_div<6>.T = clk_div<0> & clk_div<1> & clk_div<2> & 
	clk_div<3> & clk_div<4> & clk_div<5>
	# clk_div<0> & clk_div<1> & !clk_div<2> & 
	!clk_div<3> & !clk_div<4> & clk_div<5> & clk_div<6> & 
	!clk_div<7>;
   clk_div<6>.CLK = clk;
   clk_div<6>.AR = !rst;

MACROCELL | 1 | 6 | clk_div<7>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 7 | 1 | 0 | 1 | 2 | 1 | 3 | 1 | 1 | 1 | 17 | 1 | 16 | 1 | 15
INPUTS | 9 | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk  | rst
INPUTMC | 7 | 2 | 4 | 1 | 9 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15
INPUTP | 2 | 143 | 79
EQ | 4 | 
   clk_div<7>.T = clk_div<0> & clk_div<1> & clk_div<2> & 
	clk_div<3> & clk_div<4> & clk_div<5> & clk_div<6>;
   clk_div<7>.CLK = clk;
   clk_div<7>.AR = !rst;

MACROCELL | 2 | 3 | cnt_scan<0>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 13 | 3 | 8 | 3 | 10 | 3 | 13 | 2 | 13 | 2 | 12 | 1 | 5 | 1 | 4 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 16 | 3 | 17 | 3 | 9
INPUTS | 2 | clk  | rst
INPUTP | 2 | 143 | 79
EQ | 3 | 
   cnt_scan<0>.T = Vcc;
   cnt_scan<0>.CLK = clk;
   cnt_scan<0>.AR = !rst;

MACROCELL | 3 | 13 | cnt_scan<10>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 4 | 3 | 8 | 3 | 10 | 3 | 9 | 3 | 12
INPUTS | 18 | cnt_scan<0>  | cnt_scan<1>  | cnt_scan<2>  | cnt_scan<3>  | cnt_scan<4>  | cnt_scan<5>  | cnt_scan<6>  | cnt_scan<7>  | cnt_scan<8>  | cnt_scan<9>  | clk  | rst  | en<0>  | en<1>  | writeData_reg<0>  | writeData_reg<1>  | writeData_reg<2>  | writeData_reg<3>
INPUTMC | 16 | 2 | 3 | 2 | 13 | 2 | 12 | 1 | 5 | 1 | 4 | 3 | 5 | 3 | 4 | 3 | 3 | 3 | 16 | 3 | 17 | 3 | 8 | 3 | 10 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 3 | 12
EQ | 9 | 
   cnt_scan<10>.T = cnt_scan<0> & cnt_scan<1> & cnt_scan<2> & 
	cnt_scan<3> & cnt_scan<4> & cnt_scan<5> & cnt_scan<6> & 
	cnt_scan<7> & cnt_