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📄 i2c.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
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INPUTS | 5 | data_in<3>  | clk  | rst  | main_state_FFd1  | main_state_FFd2
INPUTMC | 2 | 0 | 16 | 0 | 15
INPUTP | 3 | 69 | 143 | 79
EQ | 4 | 
   writeData_reg<3>.D = data_in<3>;
   writeData_reg<3>.CLK = clk;
   writeData_reg<3>.AR = !rst;
   writeData_reg<3>.CE = !main_state_FFd1 & !main_state_FFd2;

MACROCELL | 6 | 12 | scl_xhdl1
ATTRIBUTES | 8782754 | 0
OUTPUTMC | 1 | 6 | 12
INPUTS | 7 | phase0  | phase2  | scl  | main_state_FFd1  | main_state_FFd2  | clk  | rst
INPUTMC | 5 | 1 | 3 | 1 | 1 | 6 | 12 | 0 | 16 | 0 | 15
INPUTP | 2 | 143 | 79
EQ | 5 | 
   scl.D = phase0
	# !phase2 & scl
	# !main_state_FFd1 & !main_state_FFd2;
   scl.CLK = clk;
   scl.AP = !rst;

MACROCELL | 6 | 16 | inner_state_FFd4
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 42 | 6 | 5 | 7 | 13 | 5 | 1 | 7 | 6 | 7 | 10 | 7 | 9 | 7 | 7 | 6 | 17 | 7 | 1 | 6 | 16 | 5 | 12 | 0 | 16 | 0 | 15 | 5 | 15 | 7 | 3 | 5 | 6 | 7 | 4 | 7 | 2 | 6 | 2 | 2 | 1 | 2 | 6 | 2 | 11 | 2 | 5 | 5 | 0 | 2 | 10 | 2 | 9 | 0 | 17 | 5 | 7 | 5 | 11 | 5 | 13 | 5 | 14 | 5 | 16 | 6 | 0 | 6 | 1 | 6 | 4 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 15 | 7 | 12 | 7 | 15
INPUTS | 10 | phase3  | inner_state_FFd4  | main_state_FFd1  | main_state_FFd2  | inner_state_FFd1  | inner_state_FFd3  | EXP30_.EXP  | EXP31_.EXP  | clk  | rst
INPUTMC | 8 | 1 | 0 | 6 | 16 | 0 | 16 | 0 | 15 | 5 | 12 | 5 | 15 | 6 | 15 | 6 | 17
INPUTP | 2 | 143 | 79
IMPORTS | 2 | 6 | 15 | 6 | 17
EQ | 46 | 
   inner_state_FFd4.D = !phase3 & inner_state_FFd4 & main_state_FFd1
	# !phase3 & inner_state_FFd4 & main_state_FFd2
	# inner_state_FFd1 & main_state_FFd1 & 
	inner_state_FFd3
;Imported pterms FB7_16
	# inner_state_FFd1 & main_state_FFd2 & 
	inner_state_FFd3
	# phase3 & inner_state_FFd1 & main_state_FFd1 & 
	!i2c_state_FFd3
	# inner_state_FFd4 & main_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2
	# inner_state_FFd4 & main_state_FFd2 & 
	!inner_state_FFd3 & !inner_state_FFd2
	# inner_state_FFd4 & main_state_FFd2 & 
	!i2c_state_FFd3 & i2c_state_FFd2
;Imported pterms FB7_15
	# phase3 & main_state_FFd1 & inner_state_FFd3 & 
	inner_state_FFd2 & !i2c_state_FFd2
	# phase3 & main_state_FFd2 & inner_state_FFd3 & 
	i2c_state_FFd3 & inner_state_FFd2
	# phase3 & main_state_FFd2 & inner_state_FFd3 & 
	inner_state_FFd2 & !i2c_state_FFd2
;Imported pterms FB7_18
	# phase3 & inner_state_FFd1 & main_state_FFd1 & 
	i2c_state_FFd1
	# phase3 & inner_state_FFd1 & main_state_FFd2 & 
	i2c_state_FFd3
	# phase3 & inner_state_FFd1 & main_state_FFd2 & 
	!i2c_state_FFd2
	# phase3 & main_state_FFd1 & inner_state_FFd3 & 
	!i2c_state_FFd3 & inner_state_FFd2
	# inner_state_FFd4 & main_state_FFd1 & 
	i2c_state_FFd3 & i2c_state_FFd2 & !i2c_state_FFd1
;Imported pterms FB7_1
	# phase3 & !inner_state_FFd4 & inner_state_FFd1 & 
	main_state_FFd1 & !i2c_state_FFd2
	# phase3 & main_state_FFd1 & inner_state_FFd3 & 
	inner_state_FFd2 & i2c_state_FFd1
	# phase3 & main_state_FFd1 & !inner_state_FFd3 & 
	!i2c_state_FFd3 & !inner_state_FFd2 & !i2c_state_FFd2 & link
	# phase3 & main_state_FFd1 & !inner_state_FFd3 & 
	!i2c_state_FFd3 & !inner_state_FFd2 & !i2c_state_FFd1 & link
	# phase3 & main_state_FFd2 & !inner_state_FFd3 & 
	!i2c_state_FFd3 & !inner_state_FFd2 & !i2c_state_FFd2 & link;
   inner_state_FFd4.CLK = clk;
   inner_state_FFd4.AR = !rst;

MACROCELL | 5 | 12 | inner_state_FFd1
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 42 | 6 | 5 | 7 | 13 | 5 | 1 | 7 | 6 | 7 | 10 | 7 | 9 | 7 | 7 | 6 | 17 | 7 | 1 | 6 | 16 | 5 | 12 | 0 | 16 | 0 | 15 | 5 | 15 | 7 | 3 | 5 | 6 | 7 | 4 | 7 | 2 | 6 | 3 | 2 | 1 | 4 | 17 | 2 | 11 | 2 | 5 | 2 | 10 | 2 | 9 | 0 | 17 | 5 | 5 | 5 | 7 | 5 | 11 | 5 | 13 | 5 | 14 | 5 | 16 | 6 | 0 | 6 | 1 | 6 | 2 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 15 | 7 | 12 | 7 | 15
INPUTS | 13 | phase3  | inner_state_FFd4  | inner_state_FFd1  | main_state_FFd1  | inner_state_FFd3  | i2c_state_FFd3  | inner_state_FFd2  | main_state_FFd2  | i2c_state_FFd2  | en_2_OBUF$BUF4.EXP  | clk  | rst  | EXP17_.EXP
INPUTMC | 11 | 1 | 0 | 6 | 16 | 5 | 12 | 0 | 16 | 5 | 15 | 7 | 3 | 5 | 6 | 0 | 15 | 7 | 4 | 5 | 11 | 5 | 13
INPUTP | 2 | 143 | 79
IMPORTS | 2 | 5 | 11 | 5 | 13
EQ | 28 | 
   inner_state_FFd1.T = phase3 & !inner_state_FFd4 & !inner_state_FFd1 & 
	main_state_FFd1 & !inner_state_FFd3 & !i2c_state_FFd3 & 
	inner_state_FFd2
	# phase3 & !inner_state_FFd4 & !inner_state_FFd1 & 
	main_state_FFd2 & !inner_state_FFd3 & i2c_state_FFd3 & 
	inner_state_FFd2
	# phase3 & !inner_state_FFd4 & !inner_state_FFd1 & 
	main_state_FFd2 & !inner_state_FFd3 & inner_state_FFd2 & 
	!i2c_state_FFd2
;Imported pterms FB6_12
	# phase3 & !inner_state_FFd4 & !inner_state_FFd1 & 
	main_state_FFd1 & !inner_state_FFd3 & inner_state_FFd2 & 
	i2c_state_FFd1
;Imported pterms FB6_14
	# inner_state_FFd1 & !main_state_FFd1 & 
	!main_state_FFd2
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	!main_state_FFd1 & !inner_state_FFd3 & !i2c_state_FFd2
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	!inner_state_FFd3 & !i2c_state_FFd2 & !i2c_state_FFd1
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	!main_state_FFd2 & !inner_state_FFd3 & !i2c_state_FFd3 & 
	!i2c_state_FFd1
	# phase3 & !inner_state_FFd4 & !inner_state_FFd1 & 
	main_state_FFd1 & !inner_state_FFd3 & inner_state_FFd2 & 
	!i2c_state_FFd2;
   inner_state_FFd1.CLK = clk;
   inner_state_FFd1.AR = !rst;

MACROCELL | 0 | 16 | main_state_FFd1
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 44 | 6 | 7 | 0 | 8 | 7 | 14 | 5 | 2 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 8 | 7 | 0 | 7 | 5 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 6 | 12 | 6 | 16 | 5 | 12 | 0 | 16 | 6 | 17 | 5 | 15 | 7 | 3 | 5 | 6 | 7 | 4 | 7 | 2 | 6 | 3 | 2 | 0 | 2 | 8 | 0 | 17 | 5 | 5 | 5 | 7 | 5 | 11 | 5 | 13 | 5 | 14 | 5 | 16 | 6 | 0 | 6 | 4 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 9 | 6 | 11 | 6 | 14 | 6 | 15 | 0 | 15
INPUTS | 35 | phase3  | inner_state_FFd1  | main_state_FFd1  | inner_state_FFd3  | i2c_state_FFd2  | i2c_state_FFd1  | sda  | phase1  | inner_state_FFd4  | i2c_state_FFd3  | wr_input  | cnt_delay<0>  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<18>  | cnt_delay<8>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<15>  | cnt_delay<16>  | cnt_delay<17>  | cnt_delay<19>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | cnt_delay<9>  | main_state_FFd2  | cnt_delay<15>.EXP  | clk  | rst
INPUTMC | 32 | 1 | 0 | 5 | 12 | 0 | 16 | 5 | 15 | 7 | 4 | 7 | 2 | 6 | 7 | 1 | 2 | 6 | 16 | 7 | 3 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 0 | 10 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 17
INPUTP | 3 | 112 | 143 | 79
EXPORTS | 1 | 0 | 15
IMPORTS | 1 | 0 | 17
EQ | 24 | 
   main_state_FFd1.T = phase3 & inner_state_FFd1 & main_state_FFd1 & 
	inner_state_FFd3 & i2c_state_FFd2 & i2c_state_FFd1
	# sda & phase1 & inner_state_FFd4 & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd3 & 
	!i2c_state_FFd3 & !i2c_state_FFd1
;Imported pterms FB1_18
	# sda & phase1 & inner_state_FFd4 & 
	inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd3 & 
	!i2c_state_FFd2 & !i2c_state_FFd1
	# !rd_input & wr_input & !cnt_delay<0> & 
	cnt_delay<10> & cnt_delay<12> & cnt_delay<13> & cnt_delay<18> & 
	cnt_delay<8> & !cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & 
	!cnt_delay<16> & !cnt_delay<17> & cnt_delay<19> & !cnt_delay<1> & 
	!cnt_delay<2> & !cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & 
	!cnt_delay<6> & !cnt_delay<7> & !cnt_delay<9> & !main_state_FFd1 & 
	!main_state_FFd2;
   main_state_FFd1.CLK = clk;
   main_state_FFd1.AR = !rst;
    main_state_FFd1.EXP  =  !wr_input & !cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<12> & cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & 
	!cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & 
	!cnt_delay<17> & cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & 
	!cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & 
	!cnt_delay<7> & !cnt_delay<9> & !main_state_FFd1 & !main_state_FFd2

MACROCELL | 0 | 15 | main_state_FFd2
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 36 | 6 | 7 | 0 | 8 | 2 | 17 | 2 | 16 | 2 | 15 | 2 | 14 | 6 | 12 | 6 | 16 | 5 | 12 | 6 | 17 | 0 | 15 | 5 | 15 | 7 | 3 | 5 | 6 | 7 | 4 | 7 | 2 | 6 | 3 | 2 | 7 | 5 | 0 | 0 | 16 | 0 | 17 | 5 | 7 | 5 | 13 | 5 | 14 | 5 | 16 | 6 | 0 | 6 | 2 | 6 | 4 | 6 | 5 | 6 | 6 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 14 | 6 | 15 | 7 | 14
INPUTS | 12 | main_state_FFd2  | i2c_state_FFd3  | i2c_state_FFd2  | phase3  | inner_state_FFd1  | inner_state_FFd3  | sda  | phase1  | inner_state_FFd4  | main_state_FFd1.EXP  | clk  | rst
INPUTMC | 10 | 0 | 15 | 7 | 3 | 7 | 4 | 1 | 0 | 5 | 12 | 5 | 15 | 6 | 7 | 1 | 2 | 6 | 16 | 0 | 16
INPUTP | 2 | 143 | 79
IMPORTS | 1 | 0 | 16
EQ | 15 | 
   main_state_FFd2.T = main_state_FFd2 & !i2c_state_FFd3 & 
	i2c_state_FFd2
	# phase3 & inner_state_FFd1 & main_state_FFd2 & 
	inner_state_FFd3 & i2c_state_FFd2
	# sda & phase1 & inner_state_FFd4 & 
	inner_state_FFd1 & main_state_FFd2 & !inner_state_FFd3
;Imported pterms FB1_17
	# !wr_input & !cnt_delay<0> & cnt_delay<10> & 
	cnt_delay<12> & cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & 
	!cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & 
	!cnt_delay<17> & cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & 
	!cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & 
	!cnt_delay<7> & !cnt_delay<9> & !main_state_FFd1 & !main_state_FFd2;
   main_state_FFd2.CLK = clk;
   main_state_FFd2.AR = !rst;

MACROCELL | 5 | 15 | inner_state_FFd3
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 43 | 6 | 7 | 7 | 13 | 5 | 1 | 6 | 15 | 7 | 6 | 7 | 9 | 7 | 7 | 6 | 17 | 7 | 1 | 6 | 16 | 5 | 12 | 0 | 16 | 0 | 15 | 5 | 15 | 7 | 3 | 5 | 5 | 7 | 4 | 7 | 2 | 6 | 3 | 2 | 6 | 2 | 11 | 2 | 5 | 5 | 0 | 2 | 10 | 2 | 9 | 0 | 17 | 5 | 7 | 5 | 11 | 5 | 13 | 5 | 14 | 5 | 16 | 6 | 0 | 6 | 1 | 6 | 2 | 6 | 4 | 6 | 5 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 14 | 7 | 12 | 7 | 15
INPUTS | 13 | phase3  | inner_state_FFd4  | main_state_FFd2  | inner_state_FFd3  | inner_state_FFd2  | i2c_state_FFd2  | main_state_FFd1  | inner_state_FFd1  | i2c_state_FFd1  | en_2_OBUF$BUF3.EXP  | en_2_OBUF$BUF2.EXP  | clk  | rst
INPUTMC | 11 | 1 | 0 | 6 | 16 | 0 | 15 | 5 | 15 | 5 | 6 | 7 | 4 | 0 | 16 | 5 | 12 | 7 | 2 | 5 | 14 | 5 | 16
INPUTP | 2 | 143 | 79
IMPORTS | 2 | 5 | 14 | 5 | 16
EQ | 32 | 
   inner_state_FFd3.T = phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	main_state_FFd1 & !inner_state_FFd3 & i2c_state_FFd1
	# phase3 & inner_state_FFd4 & main_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2 & !i2c_state_FFd2
	# phase3 & inner_state_FFd4 & main_state_FFd2 & 
	!inner_state_FFd3 & !inner_state_FFd2 & !i2c_state_FFd2
;Imported pterms FB6_15
	# phase3 & inner_state_FFd4 & main_state_FFd1 & 
	!inner_state_FFd3 & !i2c_state_FFd3 & !inner_state_FFd2
	# phase3 & inner_state_FFd4 & main_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2 & i2c_state_FFd1
	# phase3 & inner_state_FFd4 & main_state_FFd2 & 
	!inner_state_FFd3 & i2c_state_FFd3 & !inner_state_FFd2
	# phase3 & !phase1 & inner_state_FFd4 & 
	inner_state_FFd1 & main_state_FFd2 & !inner_state_FFd3 & 
	i2c_state_FFd3 & i2c_state_FFd2
;Imported pterms FB6_17
	# !main_state_FFd1 & !main_state_FFd2 & 
	inner_state_FFd3
	# phase3 & inner_state_FFd4 & !inner_state_FFd1 & 
	inner_state_FFd3 & inner_state_FFd2 & !i2c_state_FFd2
	# phase3 & inner_state_FFd4 & !inner_state_FFd1 & 
	!main_state_FFd1 & inner_state_FFd3 & i2c_state_FFd3 & 
	inner_state_FFd2
	# phase3 & inner_state_FFd4 & !inner_state_FFd1 & 
	!main_state_FFd2 & inner_state_FFd3 & !i2c_state_FFd3 & 
	inner_state_FFd2
	# phase3 & inner_state_FFd4 & !inner_state_FFd1 & 
	inner_state_FFd3 & i2c_state_FFd3 & inner_state_FFd2 & 
	i2c_state_FFd1;
   inner_state_FFd3.CLK = clk;
   inner_state_FFd3.AR = !rst;

MACROCELL | 7 | 3 | i2c_state_FFd3
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 27 | 6 | 6 | 6 | 15 | 5 | 12 | 0 | 16 | 0 | 15 | 5 | 14 | 7 | 3 | 5 | 5 | 7 | 4 | 7 | 2 | 6 | 3 | 2 | 10 | 6 | 17 | 5 | 7 | 5 | 13 | 5 | 16 | 6 | 0 | 6 | 1 | 6 | 2 | 6 | 4 | 6 | 5 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 14 | 7 | 14
INPUTS | 11 | main_state_FFd1  | main_state_FFd2  | i2c_state_FFd3  | phase3  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | i2c_state_FFd2  | clk  | rst  | i2c_state_FFd1.EXP
INPUTMC | 9 | 0 | 16 | 0 | 15 | 7 | 3 | 1 | 0 | 6 | 16 | 5 | 12 | 5 | 15 | 7 | 4 | 7 | 2
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 7 | 4
IMPORTS | 1 | 7 | 2
EQ | 14 | 
   i2c_state_FFd3.T = !main_state_FFd1 & !main_state_FFd2 & 
	i2c_state_FFd3
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	main_state_FFd2 & !inner_state_FFd3 & !i2c_state_FFd3 & 
	!i2c_state_FFd2
;Imported pterms FB8_3
	# phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	main_state_FFd1 & !main_state_FFd2 & !inner_state_FFd3 & 
	!i2c_state_FFd2;
   i2c_state_FFd3.CLK = clk;
   i2c_state_FFd3.AR = !rst;
    i2c_state_FFd3.EXP  =  phase3 & inner_state_FFd4 & inner_state_FFd1 & 
	main_state_FFd2 & !inner_state_FFd3 & i2c_state_FFd3 & 
	!i2c_state_FFd2

MACROCELL | 5 | 6 | inner_state_FFd2
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 36 | 6 | 7 | 7 | 13 | 5 | 1 | 7 | 6 | 7 | 10 | 7 | 9 | 7 | 7 | 6 | 17 | 7 | 1 | 6 | 15 | 5 | 12 | 5 | 15 | 5 | 6 | 6 | 3 | 4 | 17 | 2 | 11 | 2 | 9 | 5 | 5 | 5 | 7 | 5 | 11 | 5 | 13 | 5 | 14 | 5 | 16 | 6 | 0 | 6 | 1 | 6 | 2 | 6 | 4 | 6 | 5 | 6 | 6 | 6 | 8 | 6 | 9 | 6 | 10 | 6 | 11 | 6 | 14 | 7 | 12 | 7 | 15
INPUTS | 10 | main_state_FFd1  | main_state_FFd2  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd2  | phase3  | EXP16_.EXP  | _11_.EXP  | clk  | rst
INPUTMC | 8 | 0 | 16 | 0 | 15 | 6 | 16 | 5 | 12 | 5 | 6 | 1 | 0 | 5 | 5 | 5 | 7
INPUTP | 2 | 143 | 79
IMPORTS | 2 | 5 | 5 | 5 | 7
EQ | 22 | 
   !inner_state_FFd2.D = !main_state_FFd1 & !main_state_FFd2
	# !phase3 & !inner_state_FFd1 & !inner_state_FFd2
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