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📄 i2c.mfd

📁 Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档
💻 MFD
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MACROCELL | 0 | 0 | cnt_delay<9>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 0 | 0 | 17
INPUTS | 18 | cnt_delay<0>  | cnt_delay<8>  | cnt_delay<1>  | cnt_delay<2>  | cnt_delay<3>  | cnt_delay<4>  | cnt_delay<5>  | cnt_delay<6>  | cnt_delay<7>  | clk  | rst  | start_delaycnt  | cnt_delay<10>  | cnt_delay<12>  | cnt_delay<13>  | cnt_delay<11>  | cnt_delay<14>  | cnt_delay<9>
INPUTMC | 16 | 0 | 7 | 0 | 9 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 8 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 6 | 0 | 5 | 0 | 0
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 0 | 17
EQ | 10 | 
   cnt_delay<9>.T = cnt_delay<0> & cnt_delay<8> & cnt_delay<1> & 
	cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & 
	cnt_delay<6> & cnt_delay<7>;
   cnt_delay<9>.CLK = clk;
   cnt_delay<9>.AR = !rst;
   cnt_delay<9>.CE = start_delaycnt;
    cnt_delay<9>.EXP  =  cnt_delay<0> & cnt_delay<10> & cnt_delay<12> & 
	cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<14> & 
	cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & 
	cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9>

MACROCELL | 1 | 1 | phase2
ATTRIBUTES | 8520496 | 0
OUTPUTMC | 2 | 1 | 1 | 6 | 12
INPUTS | 11 | phase2  | clk_div<0>  | clk_div<1>  | clk_div<2>  | clk_div<3>  | clk_div<4>  | clk_div<5>  | clk_div<6>  | clk_div<7>  | clk  | rst
INPUTMC | 9 | 1 | 1 | 2 | 4 | 1 | 9 | 1 | 17 | 1 | 8 | 1 | 7 | 1 | 16 | 1 | 15 | 1 | 6
INPUTP | 2 | 143 | 79
EQ | 5 | 
   phase2.D = !phase2 & clk_div<0> & !clk_div<1> & !clk_div<2> & 
	!clk_div<3> & clk_div<4> & clk_div<5> & !clk_div<6> & 
	!clk_div<7>;
   phase2.CLK = clk;
   phase2.AR = !rst;

MACROCELL | 7 | 14 | readData_reg<0>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 17 | 5 | 8 | 5 | 2 | 3 | 0 | 3 | 15 | 5 | 9 | 3 | 12 | 5 | 3 | 5 | 4 | 3 | 7 | 3 | 6 | 3 | 11 | 3 | 14 | 3 | 16 | 5 | 1 | 7 | 15 | 7 | 16 | 7 | 13
INPUTS | 9 | phase3  | main_state_FFd2  | i2c_state_FFd3  | i2c_state_FFd2  | seg_data_6_OBUF.EXP  | clk  | rst  | main_state_FFd1  | i2c_state_FFd1
INPUTMC | 7 | 1 | 0 | 0 | 15 | 7 | 3 | 7 | 4 | 7 | 15 | 0 | 16 | 7 | 2
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 7 | 13
IMPORTS | 1 | 7 | 15
EQ | 14 | 
   !readData_reg<0>.T = ;Imported pterms FB8_16
	  !phase1
	# readData_reg<0> & sda.PIN
	# !readData_reg<0> & !sda.PIN
	# inner_state_FFd4 & inner_state_FFd1 & 
	inner_state_FFd2
	# !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2;
   readData_reg<0>.CLK = clk;
   readData_reg<0>.AR = !rst;
   readData_reg<0>.CE = main_state_FFd1 & i2c_state_FFd1;
    readData_reg<0>.EXP  =  !phase3 & main_state_FFd2 & i2c_state_FFd3
	# main_state_FFd1 & !i2c_state_FFd3 & 
	i2c_state_FFd2 & !i2c_state_FFd1

MACROCELL | 5 | 2 | readData_reg<1>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 5 | 2 | 5 | 10 | 3 | 0 | 3 | 15 | 5 | 8 | 3 | 12 | 5 | 1 | 7 | 13 | 3 | 7 | 3 | 6 | 3 | 11 | 3 | 14 | 3 | 16 | 5 | 4 | 7 | 16
INPUTS | 8 | phase1  | readData_reg<0>  | readData_reg<1>  | _10_.EXP  | clk  | rst  | main_state_FFd1  | i2c_state_FFd1
INPUTMC | 6 | 1 | 2 | 7 | 14 | 5 | 2 | 5 | 1 | 0 | 16 | 7 | 2
INPUTP | 2 | 143 | 79
IMPORTS | 1 | 5 | 1
EQ | 11 | 
   !readData_reg<1>.T = !phase1
	# readData_reg<0> & readData_reg<1>
;Imported pterms FB6_2
	# !readData_reg<0> & !readData_reg<1>
	# inner_state_FFd4 & inner_state_FFd1 & 
	inner_state_FFd2
	# !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2;
   readData_reg<1>.CLK = clk;
   readData_reg<1>.AR = !rst;
   readData_reg<1>.CE = main_state_FFd1 & i2c_state_FFd1;

MACROCELL | 7 | 12 | readData_reg<2>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 7 | 10 | 7 | 11 | 3 | 0 | 3 | 14 | 5 | 8 | 3 | 12 | 5 | 3 | 7 | 13 | 3 | 7 | 3 | 6 | 3 | 11 | 3 | 16 | 5 | 4 | 5 | 10 | 7 | 16
INPUTS | 10 | phase1  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd3  | inner_state_FFd2  | $OpTx$FX_DC$59.EXP  | clk  | rst  | main_state_FFd1  | i2c_state_FFd1
INPUTMC | 8 | 1 | 2 | 6 | 16 | 5 | 12 | 5 | 15 | 5 | 6 | 7 | 13 | 0 | 16 | 7 | 2
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 7 | 11
IMPORTS | 1 | 7 | 13
EQ | 13 | 
   !readData_reg<2>.T = !phase1
;Imported pterms FB8_14
	# readData_reg<1> & readData_reg<2>
	# !readData_reg<1> & !readData_reg<2>
	# inner_state_FFd4 & inner_state_FFd1 & 
	inner_state_FFd2
	# !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2;
   readData_reg<2>.CLK = clk;
   readData_reg<2>.AR = !rst;
   readData_reg<2>.CE = main_state_FFd1 & i2c_state_FFd1;
    readData_reg<2>.EXP  =  !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2

MACROCELL | 7 | 11 | readData_reg<3>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 7 | 11 | 7 | 9 | 3 | 0 | 3 | 15 | 5 | 9 | 3 | 11 | 5 | 3 | 7 | 10 | 3 | 7 | 3 | 6 | 3 | 14 | 3 | 16 | 5 | 4 | 5 | 10 | 7 | 16
INPUTS | 9 | phase1  | readData_reg<2>  | readData_reg<3>  | readData_reg<4>.EXP  | readData_reg<2>.EXP  | clk  | rst  | main_state_FFd1  | i2c_state_FFd1
INPUTMC | 7 | 1 | 2 | 7 | 12 | 7 | 11 | 7 | 10 | 7 | 12 | 0 | 16 | 7 | 2
INPUTP | 2 | 143 | 79
IMPORTS | 2 | 7 | 10 | 7 | 12
EQ | 12 | 
   !readData_reg<3>.T = !phase1
	# readData_reg<2> & readData_reg<3>
;Imported pterms FB8_11
	# !readData_reg<2> & !readData_reg<3>
	# inner_state_FFd4 & inner_state_FFd1 & 
	inner_state_FFd2
;Imported pterms FB8_13
	# !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2;
   readData_reg<3>.CLK = clk;
   readData_reg<3>.AR = !rst;
   readData_reg<3>.CE = main_state_FFd1 & i2c_state_FFd1;

MACROCELL | 7 | 10 | readData_reg<4>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 11 | 7 | 9 | 7 | 8 | 3 | 7 | 3 | 15 | 5 | 9 | 3 | 12 | 5 | 3 | 7 | 7 | 3 | 17 | 7 | 16 | 7 | 11
INPUTS | 10 | readData_reg<2>  | readData_reg<3>  | inner_state_FFd4  | inner_state_FFd1  | inner_state_FFd2  | EXP34_.EXP  | clk  | rst  | main_state_FFd1  | i2c_state_FFd1
INPUTMC | 8 | 7 | 12 | 7 | 11 | 6 | 16 | 5 | 12 | 5 | 6 | 7 | 9 | 0 | 16 | 7 | 2
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 7 | 11
IMPORTS | 1 | 7 | 9
EQ | 14 | 
   !readData_reg<4>.T = ;Imported pterms FB8_10
	  !phase1
	# readData_reg<3> & readData_reg<4>
	# !readData_reg<3> & !readData_reg<4>
	# inner_state_FFd4 & inner_state_FFd1 & 
	inner_state_FFd2
	# !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2;
   readData_reg<4>.CLK = clk;
   readData_reg<4>.AR = !rst;
   readData_reg<4>.CE = main_state_FFd1 & i2c_state_FFd1;
    readData_reg<4>.EXP  =  !readData_reg<2> & !readData_reg<3>
	# inner_state_FFd4 & inner_state_FFd1 & 
	inner_state_FFd2

MACROCELL | 7 | 8 | readData_reg<5>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 10 | 7 | 8 | 3 | 1 | 3 | 7 | 3 | 15 | 5 | 9 | 3 | 12 | 5 | 3 | 7 | 7 | 7 | 1 | 7 | 16
INPUTS | 8 | phase1  | readData_reg<4>  | readData_reg<5>  | lowbit_OBUF.EXP  | clk  | rst  | main_state_FFd1  | i2c_state_FFd1
INPUTMC | 6 | 1 | 2 | 7 | 10 | 7 | 8 | 7 | 7 | 0 | 16 | 7 | 2
INPUTP | 2 | 143 | 79
IMPORTS | 1 | 7 | 7
EQ | 11 | 
   !readData_reg<5>.T = !phase1
	# readData_reg<4> & readData_reg<5>
;Imported pterms FB8_8
	# !readData_reg<4> & !readData_reg<5>
	# inner_state_FFd4 & inner_state_FFd1 & 
	inner_state_FFd2
	# !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2;
   readData_reg<5>.CLK = clk;
   readData_reg<5>.AR = !rst;
   readData_reg<5>.CE = main_state_FFd1 & i2c_state_FFd1;

MACROCELL | 7 | 0 | readData_reg<6>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 11 | 3 | 1 | 7 | 5 | 3 | 7 | 3 | 15 | 5 | 9 | 3 | 12 | 5 | 3 | 7 | 6 | 7 | 1 | 7 | 16 | 7 | 17
INPUTS | 7 | en<0>  | en<1>  | EXP32_.EXP  | clk  | rst  | main_state_FFd1  | i2c_state_FFd1
INPUTMC | 5 | 3 | 8 | 3 | 10 | 7 | 1 | 0 | 16 | 7 | 2
INPUTP | 2 | 143 | 79
EXPORTS | 1 | 7 | 17
IMPORTS | 1 | 7 | 1
EQ | 13 | 
   !readData_reg<6>.T = ;Imported pterms FB8_2
	  !phase1
	# readData_reg<5> & readData_reg<6>
	# !readData_reg<5> & !readData_reg<6>
	# inner_state_FFd4 & inner_state_FFd1 & 
	inner_state_FFd2
	# !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2;
   readData_reg<6>.CLK = clk;
   readData_reg<6>.AR = !rst;
   readData_reg<6>.CE = main_state_FFd1 & i2c_state_FFd1;
    readData_reg<6>.EXP  =  en<0> & en<1>
	# !en<0> & !en<1>

MACROCELL | 7 | 5 | readData_reg<7>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 9 | 7 | 5 | 3 | 7 | 3 | 15 | 5 | 9 | 3 | 12 | 5 | 3 | 7 | 6 | 3 | 1 | 7 | 16
INPUTS | 8 | phase1  | readData_reg<6>  | readData_reg<7>  | EXP33_.EXP  | clk  | rst  | main_state_FFd1  | i2c_state_FFd1
INPUTMC | 6 | 1 | 2 | 7 | 0 | 7 | 5 | 7 | 6 | 0 | 16 | 7 | 2
INPUTP | 2 | 143 | 79
IMPORTS | 1 | 7 | 6
EQ | 11 | 
   !readData_reg<7>.T = !phase1
	# readData_reg<6> & readData_reg<7>
;Imported pterms FB8_7
	# !readData_reg<6> & !readData_reg<7>
	# inner_state_FFd4 & inner_state_FFd1 & 
	inner_state_FFd2
	# !inner_state_FFd4 & !inner_state_FFd1 & 
	!inner_state_FFd3 & !inner_state_FFd2;
   readData_reg<7>.CLK = clk;
   readData_reg<7>.AR = !rst;
   readData_reg<7>.CE = main_state_FFd1 & i2c_state_FFd1;

MACROCELL | 2 | 17 | writeData_reg<0>
ATTRIBUTES | 8520672 | 0
OUTPUTMC | 11 | 3 | 0 | 3 | 14 | 5 | 8 | 3 | 11 | 3 | 16 | 5 | 4 | 3 | 6 | 5 | 0 | 3 | 8 | 3 | 13 | 7 | 17
INPUTS | 5 | data_in<0>  | clk  | rst  | main_state_FFd1  | main_state_FFd2
INPUTMC | 2 | 0 | 16 | 0 | 15
INPUTP | 3 | 77 | 143 | 79
EQ | 4 | 
   writeData_reg<0>.D = data_in<0>;
   writeData_reg<0>.CLK = clk;
   writeData_reg<0>.AP = !rst;
   writeData_reg<0>.CE = !main_state_FFd1 & !main_state_FFd2;

MACROCELL | 2 | 16 | writeData_reg<1>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 13 | 3 | 0 | 3 | 14 | 5 | 8 | 3 | 11 | 3 | 17 | 5 | 10 | 3 | 6 | 5 | 0 | 3 | 8 | 3 | 13 | 3 | 16 | 5 | 4 | 7 | 17
INPUTS | 5 | data_in<1>  | clk  | rst  | main_state_FFd1  | main_state_FFd2
INPUTMC | 2 | 0 | 16 | 0 | 15
INPUTP | 3 | 74 | 143 | 79
EQ | 4 | 
   writeData_reg<1>.D = data_in<1>;
   writeData_reg<1>.CLK = clk;
   writeData_reg<1>.AR = !rst;
   writeData_reg<1>.CE = !main_state_FFd1 & !main_state_FFd2;

MACROCELL | 2 | 15 | writeData_reg<2>
ATTRIBUTES | 8520672 | 0
OUTPUTMC | 13 | 3 | 0 | 3 | 14 | 5 | 8 | 3 | 11 | 3 | 17 | 5 | 10 | 3 | 6 | 5 | 0 | 3 | 8 | 3 | 13 | 3 | 16 | 5 | 4 | 7 | 17
INPUTS | 5 | data_in<2>  | clk  | rst  | main_state_FFd1  | main_state_FFd2
INPUTMC | 2 | 0 | 16 | 0 | 15
INPUTP | 3 | 72 | 143 | 79
EQ | 4 | 
   writeData_reg<2>.D = data_in<2>;
   writeData_reg<2>.CLK = clk;
   writeData_reg<2>.AP = !rst;
   writeData_reg<2>.CE = !main_state_FFd1 & !main_state_FFd2;

MACROCELL | 2 | 14 | writeData_reg<3>
ATTRIBUTES | 8520560 | 0
OUTPUTMC | 12 | 3 | 0 | 3 | 14 | 5 | 8 | 3 | 8 | 3 | 17 | 5 | 10 | 3 | 6 | 2 | 7 | 3 | 13 | 3 | 16 | 5 | 4 | 7 | 17
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