📄 i2c.mfd
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cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> &
!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> &
!cnt_delay<9>;
cnt_delay<13>.CLK = clk;
cnt_delay<13>.AR = !rst;
cnt_delay<13>.CE = start_delaycnt;
MACROCELL | 0 | 11 | cnt_delay<18>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 10 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 10 | 0 | 16 | 0 | 17
INPUTS | 23 | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<8> | cnt_delay<11> | cnt_delay<14> | cnt_delay<15> | cnt_delay<16> | cnt_delay<17> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | cnt_delay<18> | cnt_delay<19> | clk | rst | start_delaycnt
INPUTMC | 21 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 10 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 14 |
cnt_delay<18>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> &
cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<14> &
cnt_delay<15> & cnt_delay<16> & cnt_delay<17> & cnt_delay<1> &
cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> &
cnt_delay<6> & cnt_delay<7> & cnt_delay<9>
# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> &
cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> &
!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> &
cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> &
!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> &
!cnt_delay<9>;
cnt_delay<18>.CLK = clk;
cnt_delay<18>.AR = !rst;
cnt_delay<18>.CE = start_delaycnt;
MACROCELL | 0 | 9 | cnt_delay<8>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 0 | 0 | 17
INPUTS | 23 | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<18> | cnt_delay<8> | cnt_delay<11> | cnt_delay<14> | cnt_delay<15> | cnt_delay<16> | cnt_delay<17> | cnt_delay<19> | cnt_delay<9> | clk | rst | start_delaycnt
INPUTMC | 21 | 0 | 7 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 0 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 12 |
cnt_delay<8>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2> &
cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6> &
cnt_delay<7>
# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> &
cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> &
!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> &
cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> &
!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> &
!cnt_delay<9>;
cnt_delay<8>.CLK = clk;
cnt_delay<8>.AR = !rst;
cnt_delay<8>.CE = start_delaycnt;
MACROCELL | 0 | 6 | cnt_delay<11>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 14 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 0 | 0 | 17
INPUTS | 14 | cnt_delay<0> | cnt_delay<10> | cnt_delay<8> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | clk | rst | start_delaycnt
INPUTMC | 12 | 0 | 7 | 0 | 14 | 0 | 9 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 6 |
cnt_delay<11>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<8> &
cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> &
cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9>;
cnt_delay<11>.CLK = clk;
cnt_delay<11>.AR = !rst;
cnt_delay<11>.CE = start_delaycnt;
MACROCELL | 0 | 5 | cnt_delay<14>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 13 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 0 | 0 | 17
INPUTS | 17 | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<8> | cnt_delay<11> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | clk | rst | start_delaycnt
INPUTMC | 15 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 6 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 7 |
cnt_delay<14>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> &
cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<1> &
cnt_delay<2> & cnt_delay<3> & cnt_delay<4> & cnt_delay<5> &
cnt_delay<6> & cnt_delay<7> & cnt_delay<9>;
cnt_delay<14>.CLK = clk;
cnt_delay<14>.AR = !rst;
cnt_delay<14>.CE = start_delaycnt;
MACROCELL | 0 | 17 | cnt_delay<15>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 12 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 16 | 0 | 17
INPUTS | 35 | sda | phase1 | inner_state_FFd4 | inner_state_FFd1 | main_state_FFd1 | inner_state_FFd3 | i2c_state_FFd2 | i2c_state_FFd1 | rd_input | wr_input | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<18> | clk | rst | start_delaycnt | cnt_delay<8> | cnt_delay<11> | cnt_delay<14> | cnt_delay<15> | cnt_delay<16> | cnt_delay<17> | cnt_delay<19> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | main_state_FFd2 | cnt_delay<9>.EXP
INPUTMC | 31 | 6 | 7 | 1 | 2 | 6 | 16 | 5 | 12 | 0 | 16 | 5 | 15 | 7 | 4 | 7 | 2 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 8 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 0 | 10 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 15 | 0 | 0
INPUTP | 4 | 109 | 112 | 143 | 79
EXPORTS | 1 | 0 | 16
IMPORTS | 1 | 0 | 0
EQ | 18 |
cnt_delay<15>.T = ;Imported pterms FB1_1
cnt_delay<0> & cnt_delay<10> & cnt_delay<12> &
cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<14> &
cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> &
cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9>;
cnt_delay<15>.CLK = clk;
cnt_delay<15>.AR = !rst;
cnt_delay<15>.CE = start_delaycnt;
cnt_delay<15>.EXP = sda & phase1 & inner_state_FFd4 &
inner_state_FFd1 & main_state_FFd1 & !inner_state_FFd3 &
!i2c_state_FFd2 & !i2c_state_FFd1
# !rd_input & wr_input & !cnt_delay<0> &
cnt_delay<10> & cnt_delay<12> & cnt_delay<13> & cnt_delay<18> &
cnt_delay<8> & !cnt_delay<11> & !cnt_delay<14> & !cnt_delay<15> &
!cnt_delay<16> & !cnt_delay<17> & cnt_delay<19> & !cnt_delay<1> &
!cnt_delay<2> & !cnt_delay<3> & !cnt_delay<4> & !cnt_delay<5> &
!cnt_delay<6> & !cnt_delay<7> & !cnt_delay<9> & !main_state_FFd1 &
!main_state_FFd2
MACROCELL | 0 | 4 | cnt_delay<16>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 11 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 3 | 0 | 10 | 0 | 16 | 0 | 17
INPUTS | 19 | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<8> | cnt_delay<11> | cnt_delay<14> | cnt_delay<15> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | clk | rst | start_delaycnt
INPUTMC | 17 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 17 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 8 |
cnt_delay<16>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> &
cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<14> &
cnt_delay<15> & cnt_delay<1> & cnt_delay<2> & cnt_delay<3> &
cnt_delay<4> & cnt_delay<5> & cnt_delay<6> & cnt_delay<7> &
cnt_delay<9>;
cnt_delay<16>.CLK = clk;
cnt_delay<16>.AR = !rst;
cnt_delay<16>.CE = start_delaycnt;
MACROCELL | 0 | 3 | cnt_delay<17>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 10 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 10 | 0 | 16 | 0 | 17
INPUTS | 20 | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<8> | cnt_delay<11> | cnt_delay<14> | cnt_delay<15> | cnt_delay<16> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | clk | rst | start_delaycnt
INPUTMC | 18 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 17 | 0 | 4 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 8 |
cnt_delay<17>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> &
cnt_delay<13> & cnt_delay<8> & cnt_delay<11> & cnt_delay<14> &
cnt_delay<15> & cnt_delay<16> & cnt_delay<1> & cnt_delay<2> &
cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6> &
cnt_delay<7> & cnt_delay<9>;
cnt_delay<17>.CLK = clk;
cnt_delay<17>.AR = !rst;
cnt_delay<17>.CE = start_delaycnt;
MACROCELL | 0 | 10 | cnt_delay<19>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 10 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 10 | 0 | 16 | 0 | 17
INPUTS | 23 | cnt_delay<0> | cnt_delay<10> | cnt_delay<12> | cnt_delay<13> | cnt_delay<18> | cnt_delay<8> | cnt_delay<11> | cnt_delay<14> | cnt_delay<15> | cnt_delay<16> | cnt_delay<17> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | cnt_delay<7> | cnt_delay<9> | cnt_delay<19> | clk | rst | start_delaycnt
INPUTMC | 21 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 17 | 0 | 4 | 0 | 3 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 10 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 14 |
cnt_delay<19>.T = cnt_delay<0> & cnt_delay<10> & cnt_delay<12> &
cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & cnt_delay<11> &
cnt_delay<14> & cnt_delay<15> & cnt_delay<16> & cnt_delay<17> &
cnt_delay<1> & cnt_delay<2> & cnt_delay<3> & cnt_delay<4> &
cnt_delay<5> & cnt_delay<6> & cnt_delay<7> & cnt_delay<9>
# !cnt_delay<0> & cnt_delay<10> & cnt_delay<12> &
cnt_delay<13> & cnt_delay<18> & cnt_delay<8> & !cnt_delay<11> &
!cnt_delay<14> & !cnt_delay<15> & !cnt_delay<16> & !cnt_delay<17> &
cnt_delay<19> & !cnt_delay<1> & !cnt_delay<2> & !cnt_delay<3> &
!cnt_delay<4> & !cnt_delay<5> & !cnt_delay<6> & !cnt_delay<7> &
!cnt_delay<9>;
cnt_delay<19>.CLK = clk;
cnt_delay<19>.AR = !rst;
cnt_delay<19>.CE = start_delaycnt;
MACROCELL | 1 | 14 | cnt_delay<1>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 21 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 17
INPUTS | 4 | cnt_delay<0> | clk | rst | start_delaycnt
INPUTMC | 2 | 0 | 7 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 4 |
cnt_delay<1>.T = cnt_delay<0>;
cnt_delay<1>.CLK = clk;
cnt_delay<1>.AR = !rst;
cnt_delay<1>.CE = start_delaycnt;
MACROCELL | 1 | 13 | cnt_delay<2>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 20 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 17
INPUTS | 5 | cnt_delay<0> | cnt_delay<1> | clk | rst | start_delaycnt
INPUTMC | 3 | 0 | 7 | 1 | 14 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 4 |
cnt_delay<2>.T = cnt_delay<0> & cnt_delay<1>;
cnt_delay<2>.CLK = clk;
cnt_delay<2>.AR = !rst;
cnt_delay<2>.CE = start_delaycnt;
MACROCELL | 1 | 12 | cnt_delay<3>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 19 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 17
INPUTS | 6 | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | clk | rst | start_delaycnt
INPUTMC | 4 | 0 | 7 | 1 | 14 | 1 | 13 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 4 |
cnt_delay<3>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2>;
cnt_delay<3>.CLK = clk;
cnt_delay<3>.AR = !rst;
cnt_delay<3>.CE = start_delaycnt;
MACROCELL | 1 | 11 | cnt_delay<4>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 18 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 1 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 17
INPUTS | 7 | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | clk | rst | start_delaycnt
INPUTMC | 5 | 0 | 7 | 1 | 14 | 1 | 13 | 1 | 12 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 5 |
cnt_delay<4>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2> &
cnt_delay<3>;
cnt_delay<4>.CLK = clk;
cnt_delay<4>.AR = !rst;
cnt_delay<4>.CE = start_delaycnt;
MACROCELL | 1 | 10 | cnt_delay<5>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 17 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 17
INPUTS | 8 | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | clk | rst | start_delaycnt
INPUTMC | 6 | 0 | 7 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 5 |
cnt_delay<5>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2> &
cnt_delay<3> & cnt_delay<4>;
cnt_delay<5>.CLK = clk;
cnt_delay<5>.AR = !rst;
cnt_delay<5>.CE = start_delaycnt;
MACROCELL | 0 | 2 | cnt_delay<6>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 16 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 1 | 0 | 0 | 0 | 17
INPUTS | 9 | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | clk | rst | start_delaycnt
INPUTMC | 7 | 0 | 7 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 5 |
cnt_delay<6>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2> &
cnt_delay<3> & cnt_delay<4> & cnt_delay<5>;
cnt_delay<6>.CLK = clk;
cnt_delay<6>.AR = !rst;
cnt_delay<6>.CE = start_delaycnt;
MACROCELL | 0 | 1 | cnt_delay<7>
ATTRIBUTES | 4326256 | 0
OUTPUTMC | 15 | 0 | 8 | 0 | 7 | 0 | 14 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 9 | 0 | 6 | 0 | 5 | 0 | 16 | 0 | 4 | 0 | 3 | 0 | 10 | 0 | 0 | 0 | 17
INPUTS | 10 | cnt_delay<0> | cnt_delay<1> | cnt_delay<2> | cnt_delay<3> | cnt_delay<4> | cnt_delay<5> | cnt_delay<6> | clk | rst | start_delaycnt
INPUTMC | 8 | 0 | 7 | 1 | 14 | 1 | 13 | 1 | 12 | 1 | 11 | 1 | 10 | 0 | 2 | 0 | 8
INPUTP | 2 | 143 | 79
EQ | 5 |
cnt_delay<7>.T = cnt_delay<0> & cnt_delay<1> & cnt_delay<2> &
cnt_delay<3> & cnt_delay<4> & cnt_delay<5> & cnt_delay<6>;
cnt_delay<7>.CLK = clk;
cnt_delay<7>.AR = !rst;
cnt_delay<7>.CE = start_delaycnt;
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